Researchers are also investigating other types of memories for the future. As we approach the limitations imposed by physics on charge-based memories, new architectures will be needed to scale down further. One potential memory technology that is generating some interest is magnetic nanopillars. Another commonly used acronym for nanopillar technology is RAMA. It stands for reconfigurable array of magnetic automata. Researchers have already demonstrated that a random array of up and down polarized ferromagnetic pillars (CoFe2O4) embedded in a ferroelectric or multiferroic matrix (e.g., BiFeO3) can have their magnetizations rotated from being perpendicular to the pillar (and the film) surface to being in-the-plane of the film with the application of a modest electric field.
This technique is being explored to create magnetic nanopillar devices. Wires are formed on a substrate using nanoimprint lithography, electron beam lithography, or other lithographic techniques. The ferromagnetic pillars are constructed through lithographic methods or polymeric self-assembly. The ferroelectric material resides in columns within the piezoelectric material or matrix to form potential connections between two conducting planes. The lower part of the ferromagnetic material forms the nanopillar, while the top portion is the colossal magnetocapacitive material, such as LaPrCaMnO3, LaSrMnO3 or other manganite. This material is called a colossal magnetocapacitive (CMC) material, because such a capacitor built of this compound can exhibit large changes in capacitance with changes in magnetic field. Patterning metal, etching the material where it is not needed, and depositing insulating material between the conductors form the top connections. Researchers at the University of Virginia and others have described this type of approach.
Notice that RAMA, or nanopillar technology has some potentially significant advantages over standard memory technology. The nanopillar technology can be made through polymeric self-assembly, potentially reducing the cost of the device. The cell size can be smaller, allowing for greater bit density. The switching energies are much lower than for standard memory, but the switching speeds are also much lower. RAMA can also be made to be compatible with existing CMOS processing.
Q: What types of techniques can be used to highlight bond pad cratering?
A: One technique that can highlight bond pads for cratering using an optical microscope is nickel decoration. The aluminum bondpad is etched away, and the chip is placed in a nickel plating solution for several minutes. The nickel will first adhere to the cracks, providing contrast in the optical microscope.
Please visit http://www.semitracks.com/courses/photovoltaics/thin-film-photovoltaics-technology.php to learn more about this exciting course!
(Click on each item for details).
EOS, ESD and How to Differentiate on April 4-5, 2011 in Penang, Malaysia
Wafer Fab Processing on April 25-28, 2011 in Kuala Lumpur, Malaysia
IC Packaging Metallurgy on May 9-10, 2011 in Munich, Germany
Failure and Yield Analysis on May 10-13, 2011 in Munich, Germany
Semiconductor Reliability on May 16-18, 2011 in Munich, Germany
If you have a suggestion or a comment regarding our courses, online training, discussion forums, reference materials, or if you wish to suggest a new course or location, please feel free to call us at 1-505-858-0454, or e-mail us at email@example.com.
To submit questions to the Q&A section, inquire about an article, or suggest a topic you would like to see covered in the next newsletter, please contact Jeremy Henderson by e-mail (firstname.lastname@example.org).
We are always looking for ways to enhance our courses and educational materials.
Home > Newsletters > 2011 March Newsletter