Feature Article - Future Memory Technologies, Part 3 - By Christopher Henderson

Researchers are also investigating other types of memories for the future. As we approach the limitations imposed by physics on charge-based memories, new architectures will be needed to scale down further. One potential memory technology that is generating some interest is magnetic nanopillars. Another commonly used acronym for nanopillar technology is RAMA. It stands for reconfigurable array of magnetic automata. Researchers have already demonstrated that a random array of up and down polarized ferromagnetic pillars (CoFe₂O₄) embedded in a ferroelectric or multiferroic matrix (e.g., BiFeO₃) can have their magnetizations rotated from being perpendicular to the pillar (and the film) surface to being in-the-plane of the film with the application of a modest electric field.

This technique is being explored to create magnetic nanopillar devices. Wires are formed on a substrate using nanoimprint lithography, electron beam lithography, or other lithographic techniques. The ferromagnetic pillars are constructed through lithographic methods or polymeric self-assembly. The ferroelectric material resides in columns within the piezoelectric material or matrix to form potential connections between two conducting planes. The lower part of the ferromagnetic material forms the nanopillar, while the top portion is the colossal magnetocapacitive material, such as LaPrCaMnO₃, LaSrMnO₃ or other manganite. This material is called a colossal magnetocapacitive (CMC) material, because such a capacitor built of this compound can exhibit large changes in capacitance with changes in magnetic field. Patterning metal, etching the material where it is not needed, and depositing insulating material between the conductors form the top connections. Researchers at the University of Virginia and others have described this type of approach.

Notice that RAMA, or nanopillar technology has some potentially significant advantages over standard memory technology. The nanopillar technology can be made through polymeric self-assembly, potentially reducing the cost of the device. The cell size can be smaller, allowing for greater bit density. The switching energies are much lower than for standard memory, but the switching speeds are also much lower. RAMA can also be made to be compatible with existing CMOS processing.