This month we begin a three-part series on the bumping process. Engineers use this process to electrically connect the die to a substrate, to a printed circuit board, and sometimes to connect one die to another. Here is the outline for this section. We begin by discussing the rationale for implementing bumping and why this approach is becoming quite common. We will then discuss the basic bumping process, describing the methods to attach a bump to the integrated circuit bond pad or pattern a copper pillar onto the pad. We will discuss redistribution layers that allow one to re-route the signals from the bond pads to a more area-efficient array. We will talk about bond over active circuitry, and other variants of this approach, like Bump On Pad, Bond Over Active Circuitry, and Bond Over Active Copper.
Probably the biggest driver moving the integrated circuit industry to bump processes for package connections is the need to fit into ever-tinier spaces. Many of today’s consumer electronics have limited space for components, which precludes the use of components with lead frames. The second big driver is to maximize the amount of input/output connections for a given area. If the connections only happen at the edge of the package, then one can be very limited in the number of connections to the outside world. However, an array of connections on the bottom permits more connections. The redistribution layer and bump process helps to facilitate an array of input/output connections. The third driver is high frequencies. Bump process inherently yields a package with a lower inductance level than a package with a leadframe. This provides better signal integrity, and allows one to operate at higher frequencies.
Engineers use several bump techniques or methods in the semiconductor industry. Figure 1 shows these techniques. The oldest technique is solder bumping. This can be done with lead-tin solder balls, high-lead content solder balls, and lead-free solder balls. Pad redistribution is another technique that has been around for some time. Engineers use metals like copper, and insulators like polyimide, benzocyclobutane, and polybenzoxazole deposited on top of the wafer to re-route signals to more favorable locations. Gold Bumping is another technique used to provide standoff and connection. This uses interface materials like titanium tungsten gold, or gold chromium indium for chip-on-glass, chip-on-film, and tape carrier packages. Finally, because of the high price of gold, copper pillar bumping is proliferating. There are several types of copper pillar bumping that use eutectic, high-lead, and lead-free caps.
Now let’s look a little closer at the bonding techniques, specifically the solder bumps to the printed circuit board or substrate. Figure 2 helps to illustrate the two main techniques for standard flip-chip attach. The first is the solder mask defined technique. Here we use a 20 to 30 micron thick solder mask with openings defined down to the copper layer. We then place the chip face down and reflow the solder bumps. This creates a connection with a 40 to 50 micron gap between the die and the substrate. The second is the pad defined flip-chip process. Here we have a bare copper pad on the substrate. We reflow the solder bump, which will then spread substantially, causing the standoff to collapse significantly. In this method, the gap is only 30 to 50 microns.
Let’s continue by discussing the standard bumping process. There are two primary types. One involves using fully reflowable bumps like standard 63-37 tin-lead solder, or a lead-free solder. The other involves using rigid bumps formed from a higher melting temperature material, like a high-lead or lead-free solder. Scientists allow developed other related techniques like plated bumps, screen-print bumps and solder ball preforms. The pitch, or distance between the centers of adjacent pads, varies depending on the technique. The diagram and image below show the basic solder bumping process (see Figure 3).
This sequence of steps (Figure 4) shows how one follows the standard solder bump process. This works for either a solder paste approach, or a solder ball placement approach. After wafer cleaning, one sputters the appropriate under bump metals on top of the chip and patterns these materials such that they only remain on the pads. After etching the UBM metals and removing the resist, one can place the solder ball or add the solder paste and reflow it to create the solder bump.
This sequence of steps below (Figure 5) shows how one follows a plated solder bump process. After wafer cleaning, one sputters titanium and then copper on top of the chip and patterns these materials such that they only remain on the pads. After etching the UBM metals and removing the resist, one can then expose and develop an area above the bond pads and then electro-deposit the solder. Once the solder is deposited, one can remove the resist and reflow the solder to create the solder bump.
An important consideration is the size and shape of the solder bump. With the drive towards smaller package footprints, engineers have been scaling the bumps to smaller pitches. The maximum solder bump height is typically 50% of the pitch when using standard round bumps. If one chooses plated bumps, then the pitch can be somewhat tighter due to their improved size and height consistency. However, screen print bumps are limited to the capabilities of the screen print equipment and processes. Another important aspect of the bump is the method by which one connects the bump to the pad. A solder bump does not by itself make a reliable connection to the aluminum or copper bond pad. To make a reliable connection, we need a metal system that guarantees good adhesion between the solder bump and the pad, and prevents material migration and degradation. We refer to this metal system as an under bump metallization or UBM layer. Common UBM materials include titanium-tungsten-gold for gold bumping, titanium- tungsten-copper for lead-free and lead-tin solder bumps, and titanium-copper for copper pillar bumps.
Next month, we’ll continue our discussion on the bumping process.
Alignment during lithography is a critical activity. Any type of misalignment can lead to non-functional circuits. In order to print the features on the circuit, the mask must be aligned to the wafer features. How do engineers do this? They use alignment marks printed on the wafer from the previous mask step or steps. The image below (Fig. 1) shows an example of alignment marks. Quite often, alignment marks consist of box-like structures with a cross internal to the box. The criticality of the alignment can be defined by the width of the cross in the box. A narrow cross indicates a more critical or closely aligned step. There are many types of alignment errors. The list includes mask errors, stage errors, and wafer chucking errors. These alignment errors are straightforward to understand and can usually be corrected through proper calibration and procedures. Another type of alignment error can occur from lens distortion or magnification. This type of error can be more severe, requiring one to re-polish or even replace the lens. Some alignment problems result from wafer processing. Thermal processes and the use of stressed films can produce a bow in the wafer, which leads to alignment issues. An asymmetrical resist coating can lead to depth of focus issues or refraction problems that impair alignment. Chemical mechanical polishing can lead to a non-flat wafer surface which affects alignment. Overlay metrology errors can also impact alignment.
Here are some examples of overlay errors (see Fig. 2). The blue lines represent the ideal grid and the red lines show the actual chip positions. Here we show eight different types.
Q: What is the Kooi effect?
A: The Kooi effect is also known as the white ribbons effect. It was first documented in the mid-1970s by Else Kooi, who worked at Philips Research in the Netherlands. It is the formation of a nitrogen-rich layer near the gate interface. Water oxidizes the silicon nitride mask layer, creating ammonia (NH3). The ammonia can then diffuse to the silicon interface where it forms a silicon nitride or nitrogen-rich oxide layer. This can interfere with gate oxide growth, making the gate oxide too thin in regions where the nitrogen-rich layer exists.
Please visit http://www.semitracks.com/courses/packaging/semiconductor-package-design-simulation-and-technology.php to learn more about this exciting course!
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CMOS, BiCMOS and Bipolar Process Integration on March 25-26, 2014 (Tues.-Wed.) in Austin, TX, USA
Semiconductor Package Design, Simulation and Technology on April 7-9, 2014 (Mon.-Wed.) in San Jose, CA, USA
Product Qualification on April 15-16, 2014 (Tues.-Wed.) in San Jose, CA, USA
Failure and Yield Analysis on May 5-8, 2014 (Mon.-Thurs.) in Munich, Germany
MEMS Technology on May 12-13, 2014 (Mon.-Tues.) in Munich, Germany
Semiconductor Reliability on May 12-14, 2014 (Mon.-Wed.) in Munich, Germany
Product Qualification on May 15-16, 2014 (Thurs.-Fri.) in Munich, Germany
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