Education and Training for the Electronics Industry
Semitracks provides education, training, and certification services and products for the electronics industry. We specialize in serving Semiconductor, Microsystems and Nanotechnology suppliers and users. Semitracks, Inc. helps engineers, technicians, scientists, and management understand these dynamic fields. We offer courses in Semiconductor Reliability, Test, Packaging, Process Integration, Failure and Yield Analysis, and Focused Ion Beam technology. Learn from the Experts.
A major difference between DRAMs and SRAMs is the ability of DRAM technology memory cells to be packed more densely. A big part of this advantage comes from the fact that DRAMs use one transistor and a capacitor. Another part of this advantage comes from the fact that engineers have figured out methods to pack features more closely without the corresponding improvements in lithography. A case in point is a process called borderless contacts. A nitride barrier is placed down to prevent the tungsten from making contact with the gate region. A separate lithography step is required for creating contacts to the gate regions. An etch barrier is used to equalize differences in over etch due to the topography of the CMOS transistors. In an SRAM technology, we can't allow overlap with the gate because over etch of the contact will cause a short between the junction and the gate. We also can't allow overlap with isolation because over etch of the contact will bridge around the junction causing leakage.
Semitracks' new and improved Online Training is convenient, up-to-date, and cost effective. Access the same material presented in our courses whenever you need it, right when you need it without having to worry about the high costs and hassle of traveling. The semiconductor field is an ever-changing one. With access to the most current information, you can stay on top of the new technology. Online Training is also very cost effective. For only $500 per year, you gain access to thousands of dollars worth of courses and course material.
Give our Online Training a try – for free. This month's topic is Digital Troubleshooting.
This segment is no longer available. If this topic interests you, perhaps you would be interested in our Online Training. For more information or to sign up, please visit http://www.semitracks.com/online-training/.
Semicon West 2006
July 10-14, 2006 at Moscone Center in San Francisco, CA, USA
International Symposium for Testing and Failure Analysis
November 12-16, 2006 at the Renaissance Austin Hotel in Austin, TX, USA
Semitracks, along with Semiconductor International, have put together a 1-day course on the Reliability and Characterization Challenges for Advanced Semiconductor Devices. Dr. John Suehle of the National Institute of Standards and Technology and Dr. Jeffrey Gambino of IBM, two leading researchers and lecturers in field of Semiconductor Reliability, will give an overview of the problems and reliability challenges associated with today's advanced semiconductor devices.
Dr. Suehle will cover front-end reliability issues including: High-K dielectrics, Negative Bias Temperature Instability, and Positive Bias Temperature Instability. Dr. Gambino will cover back-end process integration and reliability issues including: copper metallization, electromigration, stress induced voiding, and Low-K dielectric breakdown. The course will be held in San Francisco on Friday July 14 starting at 8:30AM going to 5:00PM with an hour and a half lunch break.
Reliability and Characterization Challenges for Advanced Semiconductor Devices on Friday July 14 at Moscone Center North Hall in San Francisco, CA, USA
Invest in yourself and your staff. Time is running short to enroll in our Summer courses on Packing Technology, Packaging Design, Process Integration, Reliability, and Failure and Yield Analysis. Come and learn from the experts!
Packaging Technology and Challenges
Semitracks, Inc. and Semiconductor International have put together a course which will provide an overview of the current business climate, anticipated trends and the associated impact on assembly/packaging roadmaps. There will be an in depth discussion of both high-end CPU roadmaps plus the roadmaps to address the multitude of communications and network devices that are driving the digital revolution.
Packaging Technology and Challenges on September 11-12, 2006 in Dallas, TX, USA
Semiconductor Process Integration
Semitracks, along with Semiconductor International, have put together a 3-day course on Semiconductor Process Integration for CMOS, Analog, and Mixed Signal Technologies. Dr. Badih El-Kareh of Texas Instruments will give an overview of the process integration challenges associated with today's advanced semiconductor devices. Dr. El-Kareh will cover passive and active components, contact and interconnect issues, isolation technologies such as STI and SOI, transistor integration issues, as well as full CMOS, BiCMOS and High-Speed Bipolar Process Integration techniques.
Process Integration on September 11-13, 2006 in Dallas, TX, USA
Packaging Design and Modeling
Semitracks, Inc. and Semiconductor International have assembled a course on IC Packaging Design and Modeling. This course provides an overview of the packaging design process. The course covers current packaging technologies, including chip scale packaging, Ball Grid Array technology and other current concepts. This class focuses on techniques and the importance of thermal and mechanical simulations. Discussions and examples will concentrate on thermal performance simulations, assembly & packaging stresses, package reliability (including solder joint fatigue simulation), and interactions between chip and package. In addition, a special section will be examples of successful wafer level simulations.
Packaging Design and Modeling on September 13-15, 2006 in Dallas, TX, USA
Semiconductor reliability is at a crossroads. In the past, reliability meant discovering, characterizing and modeling failure mechanisms and determining their impact on the reliability of the circuit. Today, reliability can involve tradeoffs between performance and reliability, assessing the impact of new materials, dealing with limited margins, etc. Analysis and experimentation is now performed at the wafer level instead of the packaging level. This requires knowledge of subjects like: design of experiments, testing, technology, processing, materials science, chemistry, and customer expectations. While reliability levels are at an all-time high level in the industry, rapid changes may quickly cause reliability to deteriorate. Your industry needs competent engineers and scientists to help solve these problems.
Semiconductor Reliability on September 25-27, 2006 in Boston, MA, USA
Failure and Yield Analysis
Failure and Yield Analysis is an increasingly difficult and complex process; engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform failure analysis. This requires knowledge of subjects like: design, testing, technology, processing, materials science, chemistry, and even optics! Failed devices and low yields can lead to customer returns and idle manufacturing lines that can cost a company millions of dollars a day. Your industry needs competent analysts to help solve these problems. This is a multi-day course that offers detailed instruction on a variety of effective tools, as well as the overall process flow for locating and characterizing the defect responsible for the failure.
Failure and Yield Analysis on September 18-21, 2006 in Boston, MA, USA
If you have a suggestion or a comment regarding our courses, online training, discussion forums, reference materials, or if you wish to suggest a new course or location, please feel free to call us at 1-505-858-0454, or e-mail us at firstname.lastname@example.org.
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