Education and Training for the Electronics Industry
Semitracks provides education, training, and certification services and products for the electronics industry. We specialize in serving Semiconductor, Microsystems and Nanotechnology suppliers and users. Semitracks, Inc. helps engineers, technicians, scientists, and management understand these dynamic fields. We offer courses in Semiconductor Reliability, Test, Packaging, Process Integration, Failure and Yield Analysis, and Focused Ion Beam technology. Learn from the Experts.
One of the biggest problems with sputter deposition is filling contacts and vias. The larger the step height or aspect ratio is, the bigger the challenge to properly fill the contact or via. Some undesirable effects include thinning, cracking, and overhangs. The overhang is sometimes referred to as breadloafing, named for the shape that bread makes when it expands past the top of its baking pan. While heating wafers improves step coverage, it does not solve the problem. The material entering a recessed feature (e.g., via or contact) must be spread over all surfaces of the feature (5 sides); this decreases the deposited film thickness per unit area. It is progressively more difficult to fill holes as aspect ratio increases. The film deposition rate is higher at top corners of holes because atoms arrive here from a larger range of angles. This produces an overhang that can cause several serious problems. The deposition rate on sidewalls decreases with time, and shadowing limits deposition on the bottom corners of hole. Eventually the hole closes completely, causing a void.
One solution is collimated sputtering. A metal honeycomb collimator is inserted between target and wafer. It traps oblique-angle vapor atoms, reducing the number of atoms hitting the surface at oblique angles. The aspect ratio of collimator is normally adjustable. This technique has several negative consequences. First, it significantly reduces deposition rate, making for longer deposition times. Second, the deposition rate decreases with time as collimator become coated. And third, the collimator must be replaced frequently.
Another solution is long throw collimated sputtering. In this approach, no physical collimator used. Instead the target-wafer separation increased from ~ 5 cm to ~ 30 cm. The oblique-angled vapor atoms never reach the wafer, striking the chamber walls instead. The pressure lowered to ~0.1 mtorr to increase the mean-free path of the atoms. The disadvantage of this technique is that the cross-wafer uniformity of hole filling is not ideal.
A third solution that is used for used for processes below the 0.25µm node where aspect ratios > 3:1 is ionized sputtering. In this technique, the sputtered atoms are ionized in flight. A bias on wafer controls energy & direction of these ions. There are several advantages, including excellent hole filling, no overhang, longer target life, and less frequent chamber cleaning. The disadvantages to this technique are more complex equipment, and a more expensive process.
Semitracks' new and improved Online Training is convenient, up-to-date, and cost effective. Access the same material presented in our courses whenever you need it, right when you need it without having to worry about the high costs and hassle of traveling. The semiconductor field is an ever-changing one. With access to the most current information, you can stay on top of the new technology. Online Training is also very cost effective. For only $500 per year, you gain access to thousands of dollars worth of courses and course material.
Give our Online Training a try – for free. This month's topic is Lead Free Issues in Semiconductor Packaging.
This segment is no longer available. If this topic interests you, perhaps you would be interested in our Online Training. For more information or to sign up, please visit http://www.semitracks.com/online-training/.
Reliability Challenges for Advanced ICs
The continued scaling of gate dielectric thickness has resulted in increased leakage current and shrinking reliability margins. Designers must balance circuit performance with device reliability. The introduction of high-k dielectric materials to reduce gate leakage current presents significant challenges for electrical and reliability characterization. Bulk trapping complicates electrical measurements and wear-out mechanisms are not yet understood. An overview of thin gate oxide reliability will be presented and issues relating to high-k gate oxide reliability will be discussed.
The scaling of transistors exacerbates hot carrier effects. One particularly difficult challenge is overcoming the effects of Negative Bias Temperature Instability (NBTI), and more recently, Positive Bias Temperature Instability (PBTI). Both NBTI and PBTI can degrade the performance of the p-channel transistor. Boron penetration from the polysilicon gate strongly affects NBTI. Both are also difficult to combat through standard processing techniques.
To improve IC performance, copper metallization and Low-K dielectrics are routinely used in advanced processes. Copper metallization exhibits different electromigration, stress voiding and corrosion behavior than traditional aluminum-based interconnect systems. The mechanical, thermal, and electrical issues due to copper and its integration with Low-K dielectrics will be discussed. Low-K dielectrics exhibit inferior thermal, mechanical, and dielectric breakdown characteristics compared to traditional silicon dioxide and silicon nitride-based materials.
Dr. John Suehle of the National Institute of Standards and Technology and Dr. Jeffrey Gambino of IBM, two leading researchers and lecturers in field of Semiconductor Reliability, will give an overview of the problems and reliability challenges associated with today's advanced semiconductor devices. Dr. Suehle will cover front-end reliability issues including: High-K dielectrics, Negative Bias Temperature Instability, and Positive Bias Temperature Instability. Dr. Gambino will cover back-end reliability issues including: copper metallization, electromigration, stress induced voiding, and Low-K dielectric breakdown.
Reliability and Characterization Challenges for Advanced ICs on July 17, 2007 in San Francisco, CA, USA at Moscone Center - Semicon West
Advanced Thermal Management and Packaging Materials
Advanced materials are becoming critical for today's microelectronic systems. As new, more powerful chip designs are introduced, they consume more power. This has made thermal management an important concern in today's high performance systems. Systems ranging from active electronically scanned radar arrays to web servers require components that can dissipate heat efficiently. This requires materials capable of dissipating heat and maintaining compatibility with the package and die.
In response to critical needs, there have been revolutionary advances in thermal management materials in the last few years. There are now over 15 low-CTE, low-density materials with thermal conductivities ranging between 400 and 1700 W/m-K, and many others with somewhat lower conductivities. Some are low cost. Others have the potential to be low cost in high-volume. Production applications include servers, laptops, PCBs, PCB cold plates/heat spreaders, cellular telephone base stations, hybrid electric vehicles, power modules, phased array antennas, thermal interface materials (TIMs), optoelectronic telecommunication packages, laser diode and LED packages, and plasma displays.
This course covers the large and increasing number of advanced thermal management materials, providing an in-depth discussion of properties, manufacturing processes, applications, cost, lessons learned, typical development programs, and future directions. Traditional materials are discussed for reference. Participants are invited to bring their thermal management problems for discussion.
Advanced Thermal Management and Packaging Materials on July 18, 2007 in San Francisco, CA, USA at Moscone Center - Semicon West
Invest in yourself and your staff. Our Summer and Fall 2007 schedule is now available, come and learn from the experts!
CMOS and BiCMOS Process Integration
Semitracks has put together a 3-day course on Semiconductor Process Integration for CMOS and BiCMOS Technologies. Dr. Badih El-Kareh, an independent consultant and the architect of numerous CMOS and BiCMOS processes, will give an overview of the process integration challenges associated with today's advanced semiconductor devices. Dr. El-Kareh will cover passive and active components, contact and interconnect issues, isolation technologies such as STI and SOI, transistor integration issues, as well as full CMOS, BiCMOS and high speed bipolar process integration techniques. Learn from one of the industry leaders on this topic.
Process Integration on September 24-26, 2007 in Dresden, Germany and on October 22-24, 2007 in Austin, TX, USA
Wafer Fab Processing
This new intensive 4-day course offers a comprehensive examination of the wafer fab processes used to manufacture state-of-the-art microchips. Topics include semiconductor devices and ICs, silicon crystal growth and crystal defects, ion implantation, thermal processing, contamination control, wafer cleaning, LPCVD, PECVD, PVD, CMP, microlithography, etch, multilevel interconnect technology, and manufacturing technology. Process integration will be illustrated using a basic CMOS process flow.
The course is designed primarily for process engineers and process technicians. The emphasis is on understanding how each individual process step works, and understanding the key process control variables for each step. The functional design of the process tools is also discussed, as are process characterization, monitoring, and control.
Engineers new to semiconductor manufacturing will gain a solid, broad understanding of the entire wafer fab process. Engineers experienced in one or more functional areas of wafer fab will benefit from a thorough understanding of processes in other areas, as well as a better appreciation of process interactions.
Each student will also receive a copy of Microchip Manufacturing by Stan Wolf. This unique, full color book is a "must have" reference text for anyone working in the semiconductor industry.
Semiconductor Processing on September 17-20, 2007 in Dresden, Germany and on October 15-18, 2007 in Austin, TX, USA
Failure and Yield Analysis
Semitracks, along with Test and Measurement World, have put together a 4-day course on Failure and Yield Analysis. Failure and Yield Analysis is an increasingly difficult and complex process; engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform failure analysis. This requires knowledge of subjects like: design, testing, technology, processing, materials science, chemistry, and even optics! Failed devices and low yields can lead to customer returns and idle manufacturing lines that can cost a company millions of dollars a day. Your industry needs competent analysts to help solve these problems. This is a multi-day course that offers detailed instruction on a variety of effective tools, as well as the overall process flow for locating and characterizing the defect responsible for the failure.
Failure and Yield Analysis on June 18-22, 2007 in Penang, Malaysia; on July 2-6, 2007 in Shanghai, China and on July 9-13, 2007 in Bangkok, Thailand
If you have a suggestion or a comment regarding our courses, online training, discussion forums, reference materials, or if you wish to suggest a new course or location, please feel free to call us at 1-505-858-0454, or e-mail us at firstname.lastname@example.org.
Home > Newsletters > 2007 May Newsletter