The second part of this series covers soft ESD failure mechanisms in plastic packages. In this article, we cover three case histories where charging was found to be a problem in plastic-packaged components. The first occurred in 1988 at Signetics during solder reflow in Japan. The second occurred at Delco, the electronics subsidiary of General Motors, in 1993. This work was the first to be published at a public conference. In fact, this group of failures led to the generation of an Automotive Electronics Council specification to diagnose and mitigate the problem. The third failure occurred in 1999 in ICs mounted next to high voltage television tubes.
One of the earliest reports of plastic package failures due to charging, or soft ESD, was at Signetics assembly operations in Japan. Their factories reported plastic-packaged components failing after board reflow assembly. Some components recovered when removed from the printed circuit boards while others did not. These components exhibited high supply current and some leakage on certain I/O pins. The components did not recover with a short, low temperature bake (70 degrees centigrade for 12 hours) but did recover with a higher temperature bake (150 degrees centigrade for 16 hours). All failed components that were decapsulated recovered immediately upon decapsulation. These components also recovered when exposed to x-ray radiation at 110 kV accelerating voltage for 12 minutes. The problem was eventually fixed by installing charge neutralization on the reflow furnaces.
The engineers at Signetics traced the problem to air flow across the surface of the plastic packages that resulted in triboelectric charging. Air flow in the ovens caused the top of the IC package to be charged to a negative voltage around -5kV. During the reflow operation, the epoxy becomes somewhat conductive, allowing charge to work through the package to the die glassivation layer and charge that layer negative. When the component cools after the reflow operation, the charge is trapped on the surface of the passivation as the epoxy returns to a more electrically insulating state. The charge on the passivation affects the transistors and parasitic structures on the IC, creating leakage on the supplies and at the I/O pins.
The charge inverts the n-epitaxial region, causing p-implanted resistors to become leaky to the p-isolation regions. The charging also changes the resistor values and transistor characteristics. Specifically, in the transistors, it led to changes in the low current beta values. The charging also created increased junction leakage and lower junction breakdown voltages.
Figure 1 illustrates the behavior of the plastic and the glassivation layer. The top of the package is charged triboelectrically. The glassivation layer forms a capacitor. The epoxy thermoset forms a variable resistor; as the temperature increases, the resistivity of the epoxy decreases, allowing the capacitor to charge. When the epoxy cools, it becomes an insulating material and traps the charge on the glassivation layer, which is still acting like a capacitor. The active structures on the die are then affected by the charge on the top of the glassivation layer. Engineers at NXP refined this model and presented their work at the 2008 International Reliability Physics Symposium. For more information, see M. van Soestbergen, et. al., "Electrical Characterization of Plastic Encapsulation Using an Alternative Gate Leakage Method," Proc. IRPS, 2008, pp. 462-467.
Even the purest of epoxies exhibits a low level of ionic contamination. As the epoxies are heated, the ionic contaminants begin to move about more easily, lowering the effective resistance of the material. On the following page, Table 1 shows the effective resistance of five types of epoxies at seven different temperatures ranging from 50 degrees to 200 degrees centigrade. Table 2 shows the times required to charge the die surface to 100 volts for the same epoxies and the same seven temperatures. At high temperatures, the die surface can charge in less than one second.
Figure 2 shows the epoxy resistances plotted in terms of resistance as a function of temperature. As the epoxies heat through the glass transition temperature, the resistance begins to drop more markedly.
Figure 3 shows the time to charge data as a function of temperature. The time to charge drops dramatically as the temperature increases. For this experiment, the engineers at Signetics used the following parameters: a 0.25 x 0.25 cm die in the package, a .095cm-thick plastic over the die, a lid voltage of 5000 volts, a 2-micron-thick passivation, and a 1-dimensional model with no lateral bleed.
In the 1980s, when several electronics subsidiaries of major automotive manufacturers encountered a soft ESD failure mechanism, they devised a test to rate components for gate leakage sensitivity that was included in the AEC Q100-006 specification. The test places a needle probe source with a high voltage on the lid of the package. The components sit on a grounded plate in an oven and are heated to a specified temperature. The voltage is applied to the lid, the components are cooled to room temperature, and, finally, they are measured for leakage. The test normally applies 400 volts to the lid. Figure 4 shows the probe needle inside the oven (left) and a close up view of the needle (right) with respect to the component.
Engineers and scientists at NXP proposed an alternative method for measuring gate leakage at IRPS in 2008. They determined that better gate leakage results occur if the post mold cure temperature is increased. Raising the temperature from 175°C to 190°C appears to tie up mobile ions in the mold compound more effectively. However, higher temperatures can lead to increased bondwire intermetallic formation. Many researchers question the merit of changing the process since these failures tend to be marginal instances of minor leakage. No field failures have been observed. Furthermore, affected ICs would get better in the field. Finally, the test methods to identify this mechanism have problems, such as slow throughput and long test times.
A number of issues occur with the proposed test method. The specification calls for setting the voltage on the lid to -400 volts, but there is no way to precisely measure the voltage since the probe influences the measurement. The proposed system for grading gate leakage on the components is not consistent. The times and temperatures for the charging conditions are arbitrary. There is no turnkey test system available. Furthermore, not much data chronicles how manufacturing problems related to components passing or not passing the gate leakage test. Finally, there is no practical solution other than adding another metal layer to the IC or package for field plating. This step would increase component costs substantially.
The diagram on the following page shows some of the problems associated with the voltage measurement. A Fluke high voltage probe is used to measure the potential at a certain height over the component. However, one typically encounters a steep voltage drop when moving away from the center position under the electrode. This is different than one would expect based on field lines.
Another potential problem with the gate leakage specification is the presence of a delamination between the package and die, or lack thereof. The delamination adds another capacitive element into the circuit, fundamentally altering the voltage that couples to the IC glassivation layer.
The third case history associated with the soft ESD mechanism in plastic packages is a Philips Semiconductor high voltage analog component. Engineers at Philips discovered this device was failing during biased temperature testing. The components exhibited bipolar base channel leakage and collector-emitter leakage. As a result, a parametric shift or functional failure occurred in the analog section. The problem worsens if the high voltage bond pad is near a sensitive analog circuit node. The charge can also spread through the plastic during burn-in or operation. Like the gate leakage problem just discussed, sensitive transistors can be found using a high voltage probe as a stimulus. Engineers have done limited studies on this mechanism, but the indications are that this mechanism is strongly accelerated by temperature. The activation energy is approximately 2.5 electron-volts, which is similar to hydrogen-based ionic movement. The problem can be mitigated by using field plating on the die layout or by using a die coat.
The trend in the semiconductor industry is toward thinner packages and larger die. In a thin package, it is easier to charge the die glassivation due to lower resistance path through the plastic to the die. With a larger die, the center of the die is farther from the bond wires that could bleed off some charge, so therefore it is more likely to store charge. Another important trend is toward lead-free components. A lead free process is hotter, so the epoxy is more conductive and quicker to pick up charge. However, it is also quicker to lose it when cooling down, unless popcorn delaminations have occurred. More metal layers improve shielding from the charge and new processes have higher doping and are less surface sensitive.
Here is a summary of soft ESD failures. The electrical symptoms include I/O leakage due to increased transistor channel currents, abnormal characteristics on unrelated circuit blocks, and higher than normal supply currents. The circumstantial symptoms include multiple failures at electrical test after packaging, or board assembly, components that initially pass, then fail a subsequent test, and components with thin glassivation or packaged in thinner packages. Some other failure mode characteristics include recovery after x-ray radiography, recovery after decapsulation, and the ability to duplicate the failure mode with a static gun after decapsulation.
Some areas of uncertainty and further research include the conduction process in epoxy and the choice between low and high conduction plastics, lead free processes, popcorn delamination, and triboelectric charging during board assembly, including sources and effective remedies.
This chart illustrates the package development process and the laboratory and research efforts that support it. Thermal modeling and laboratory work involve tasks such as thermal and computational fluid dynamics simulations, wind tunnel tests, and VXI systems for data capture. Electrical modeling and laboratory work include computer-aided drawing to computer-aided engineering translators, physics modeling through simulators like HFSS, electrical circuit modeling through SPICE simulation, electrical computer-aided design drawings, and laboratory testing using network analyzers, time domain reflectometry, and other tools. Mechanical modeling and laboratory work includes development of mechanical CAD drawings, mechanical and drop test simulations, as well as Moire interferometry measurements for stress and electromigration testing. Materials characterization lab work includes the use of techniques like thermo-mechanical analysis, differential scanning calorimetry, fourier transform infrared spectroscopy, gas chromatograph mass spectroscopy, atomic force micorscopy and Auger electron spectroscopy. Failure analysis lab work includes techniques like radiography, acoustic microscopy, energy dispersive spectroscopy, x-ray photoelectron spectroscopy and secondary ion mass spectroscopy. Further collaborations with universities and national labs may be necessary for new, high-risk development efforts.
Q: Why is Latchup testing sometimes performed at high temperatures?
A: Latchup depends on temperature, as shown by several studies of electrically induced latchup by Shoucair and Kolasinsky. The triggering current for electrically induced latchup decreases more than a factor of two as the temperature of latchup test structures is increased from 300 to 400 K. The main reason for this dependence is the increase in well resistance (it approximately doubles), with some additional contribution from the decreased forward voltage at high temperature.
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Wafer Fab Processing on June 14-17, 2010 in Enschede, Netherlands
Photovoltaics Overview on July 12, 2010 in San Francisco, CA, USA
Photovoltaics Technology and Manufacturing on July 13, 2010 in San Francisco, CA, USA
Reliability and Characterization Challenges on July 15, 2010 in San Francisco, CA, USA
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