In Part III this month, we will discuss the redistribution layer process. The drawing on the left shows a standard RDL process flow. We begin by depositing an overlying thick dielectric layer using a material like polyimide or benzocyclobutane. Next we deposit a seed layer, then electro-deposit copper, then nickel, followed by lithography and patterning to create the redistribution metal line. We then deposit a second layer of dielectric and open a window where the bump will be located. We can then place the bump at this new location. The advantages to this process include the ability to use one silicon design for multiple applications and use flip-chip and wafer layer chip scale packages. The disadvantage is that the additional mask layers and processing raise the cost of the circuit and lower the final yield (see Figure 1).
In terms of cost, moving from a situation with the ball directly attached to the pad, or bump on pad, to redistribution without a buffer dielectric, to redistribution with a buffer dielectric, raises the complexity and therefore the cost of the component. This may require some trade-offs.
Solder bumps do not only bond to the printed circuit board, but they can also be used to bond one die to another. The bonding techniques fall into three categories: thermocompression, reflow, and direct chip attach. Thermocompression uses temperature and force and some form of gap control. With reflow, one can use temperature and gap control, or temperature and the introduction of a flux. For direct chip attach, one uses low force. The blue boxes indicate the types of solders used in the various processes. Thermocompression works well with gold, indium and copper bumps and several alloys, while reflow can be used with lead-tin materials as well. For direct chip attach, there is no intermediate layer. The build-up of materials on the bond pads make direct contact to each other.
Redistribution layer techniques work best at the wafer level. This requires an equipment set and process flow that can handle full wafers. The fab-like environment may not need the same level of cleanliness as a front-end fab, but it still requires wafer-level processing techniques. This diagram shows the basic process flow with the interface between front-end and back-end identified. In this approach there is no test after saw, so it requires extensive testing beforehand. The backside coat is to provide for marking and to suppress cracking.
This is an example of a package that uses a bump process. This is the Micro-star BGA package from Texas Instruments. We show a cut-away view to expose the construction of the package traces and solder bumps. The slant in the mold compound allows for easier release from the mold forms. The Micro-star BGA uses a polyimide substrate. Some BGA formats use bizmaleimide triazine.
As we scale to smaller packages, one change that can be beneficial from a space standpoint is going to a lower profile bump. If we look at these cross-sections, notice that a solder ball produces a thicker package while bumps permit a thinner package. The land grid array (LGA) is a packaging technology with a square grid of contacts on the underside of a package. The contacts are to be connected to a grid of contacts on the PCB. Not all rows and columns of the grid need to be used. The contacts can either be made by using an LGA socket, or by using solder paste. LGA packaging is related to ball grid array (BGA) and pin grid array (PGA) packaging. Unlike pin grid arrays, land grid array packages are designed to fit both in a socket or be soldered down using surface mount technology. PGA packages cannot be soldered down using surface mount technology. In contrast with a BGA, land grid array packages in non-socketed configurations have no balls and use a flat contact which is soldered directly to the PCB and BGA packages have balls as their contacts in between the IC and the PCBs.
To summarize our three-part series, we discussed the basic bumping process. This method is increasingly used when engineers must place a component in a design with limited space. There are two major methods: using solder balls and copper pillars. We also discussed redistribution layer techniques, as these methods can allow retargeting of dice in multiple applications and target smaller footprints as well. Miniaturization is driving the need for even smaller features. This will require finer pitches and lower profiles. This means that engineers will increasingly use technologies like copper pillar bumps to fit in these tight spaces.
RESURF (also spelled without capital letters as resurf) stands for reduced surface field. This is a concept that takes advantage of the behavior of the depletion region in a p/n junction when one of the materials is confined. The following two figures show the principle behind RESURF. The basic device structure is shown here. It consists of a high voltage diode on a lightly doped p- substrate with a slightly higher-doped epitaxial n- layer on it, which is laterally bounded by a p+ isolation diffusion, shown on the left. The diode therefore consists of two parts: a lateral diode with a vertical n-/p+ boundary and possible lateral breakdown, and a vertical diode with a horizontal n-/p- boundary and possible vertical breakdown. For a thick epitaxial layer (~50μm) the breakdown voltage is ~500V and the maximum field is at the surface at the n-/p+ junction. The light magenta color denotes the depletion region in both images. Notice that the lateral electrical field EL is high near the n-/p+ junction (left image).
For a much thinner epitaxial layer (~15μm) the depletion layer of the vertical n-/p- junction influences the lateral depletion layer, and reducing the surface field (right image). Since the depletion region consumes the entire n- epi region, the electrical field behavior is much different. This is a two-dimensional effect. At a higher voltage (~1200V) the field at the surface has 2 peaks, one originating from the n-/p+ junction and another just below the surface at the curvature of the n+/n- junction, with a moderate field in between. Notice that the lateral electrical E sub L is much smaller near the n-/p+ junction. This not only supports higher breakdown voltages in the structure, but reduces hot carrier damage in the oxide near the n-/p+ junction. If the lateral distance is sufficient, breakdown only occurs vertically in the semiconductor body under the n+ region. Many power semiconductor manufacturers use this technique to create higher performance devices and improve the reliability as well. However, there are some negative effects, like the emergence of the Kirk effect at the n-/n+ junction. RESURF also impacts RDS(ON), but this can in many instances be optimized by adjusting the layout, technology dimensions, and the doping levels. RESURF techniques can be used for discrete transistors, like power npn or pnp transistors, vertical DMOS (VDMOS) devices and lateral DMOS (LDMOS) devices.
Q: I seem to recall that the makers of PIND equipment had a tape for gettering loose material when using the PIND system with the top perforated, or with the top open as a cleaning step. Who supplies that tape?
A: There really isn't a “special” brand of tape for this work. Most analysts will simply use a heavy duty double-backed adhesive tape from a manufacturer like 3M. The main issue is examination of the particles. Double-backed tape will outgas when placed in the SEM, so pump down, especially in a Field Emission SEM, where one requires lower vacuum levels. For specific recommendations though, one might contact Spectral Dynamics (http://www.spectraldynamics.com/). They sell acoustical tape circles that might work well for these applications.
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