Issue 1 Analysis - The Current Situation
Today’s analyst faces a much different situation than the analyst of the late 1960’s. While we still have standard digital logic circuits like the quad, two- input NAND gate, we also have integrated circuits that exceed 10 million gates. In addition the bipolar silicon circuits of the late 1960’s, we have a bewildering array of technologies, such as complementary metal oxide semiconductor (CMOS) circuits, BiCMOS circuits, gallium arsenide circuits, indium phosphide circuits, silicon carbide transistors, gallium nitride diodes, complex heterojunction structures, and microelectromechanical systems (MEMS). We also have a variety of design complexities, including discrete components, digital circuits, analog circuits, memory circuits, MEMS devices, radio frequency and optoelectronic components.
An example of the circuits analysts now face is shown in Figure 2.
Today’s analyst also faces more complex equipment sets. In addition to the curve tracer, optical microscope and decapsulation tools, the analyst must be familiar with a variety of electrical testing hardware, endless electrical fixture configurations, x-ray and acoustic microscopy, electron beam tools, optical beam tools, thermal detection techniques, the focused ion beam (FIB), the scanning probe/atomic force microscope, and a bevy of surface science tools. Many times, the analyst must make do with a limited set of tools, as the cost of purchasing these tools exceeds the budget of all but the most lavishly funded operations.
Today’s analyst also faces enormous pressures from the customer. The customer wants an answer to the problem immediately. Even so, there may be little, if any, ability to impact the manufacturing process. Because product cycle times are so short, many components are manufactured with a few wafer runs and are not manufactured again. The analyst’s company may not even manufacture the device; it may be sent to a foundry for fabrication. The analyst may be doing activities other than analyzing field return failures. He or she may be performing design debug, yield improvement, or qualification analysis.
Today’s analyst must know a staggering amount of information and be able to lucidly process that information to successfully guide an analysis through to completion. While the analyst of the late 1960’s could get by with a basic understanding of design, test, packaging, and some analysis tools and techniques, today’s analyst must know a whole lot more. We are expected to understand the correlation between the design and layout of multi- million transistor circuits, even though the design engineers can’t perform that task (all they know anymore is VHSIC Hardware Description Language (VHDL), Register Transfer Language (RTL), and other abstraction languages). We are expected to understand how to test complex integrated circuits, even though the test engineering community cannot figure out how to adequately test these devices. We are expected to have non-destructive depackaging techniques available for an ever-increasing number of package configurations, even though the packaging engineers cannot successfully rework these configurations. We have to understand obscure properties like the Franz-Keldyish effect, the Seebeck effect, and escape peaks.
The task of performing failure analysis is daunting. Over a career, an analyst is likely to experience many of these issues listed above. Education and training play an important role if the analyst is to be successful in his or her work. How do we prepare analysts for this environment? Please read next month's issue to see the approach to succeed in this seemingly impossible environment.
Q: Sometimes I see i/(n+0.5) used for median ranks, and other times I see (i- 0.3)/(n+0.4) used for cumulative probability in probability plots. Is one better than the other?
A: The second formula (i-0.3)/(n+0.4) is the more accurate approach. If you scale down to a sample size of 1, it correctly resolves to 0.5 for a cumulative probability. i/(n+0.5) resolves to 0.66, which is not as accurate. If you are doing calculations by hand, then i/(n+0.5) is quicker, but since most people will use a program like Excel or Relex to do these calculations, it is better to use (i- 0.3)/(n+0.4).
(Click on each item for details).
ESD Design and Technology on December 14-16, 2010 in Kuala Lumpur, Malaysia
Failure and Yield Analysis on January 18-21, 2011 in Kuala Lumpur, Malaysia
IC Packaging Metallurgy on January 24-25, 2011 in San Jose, CA, USA
If you have a suggestion or a comment regarding our courses, online training, discussion forums, reference materials, or if you wish to suggest a new course or location, please feel free to call us at 1-505-858-0454, or e-mail us at email@example.com.
To submit questions to the Q&A section, inquire about an article, or suggest a topic you would like to see covered in the next newsletter, please contact Jeremy Henderson by e-mail (firstname.lastname@example.org).
We are always looking for ways to enhance our courses and educational materials.
Home > Newsletters > 2010 November Newsletter