Finally, we describe an implementation of a double raised source/drain structure on an SOI substrate. One starts with an ultra-thin SOI wafer and performs trench isolation, channel implant, grows the gate oxide and patterns the gate. An offset spacer is grown to isolate the raised source/drain regions from the gate. Next, selective silicon growth forms the double-raised structure. This is followed by the extension implant and main spacer. Next, selective silicon growth forms the single and double-raised structure, followed by drain/source implant and anneal. One then deposits the metal for silicidation and anneals the structure. This method has been demonstrated on a logic process with embedded SRAM. It reduces the series resistance in a fully depleted SOI structure, improving the ring oscillator speed by almost 25%.
In the next issue we’ll describe other techniques used on source/drain regions, like co-implantation of inactive species, carbon implants, and Schottky barrier structures.
Thermomechanical stress in components can lead to some interesting failure mechanisms. An example of this is a mechanism called aluminum sliding. This was first reported in the early 1990s by Intel, but more recently, some companies have experienced a resurgence in this problem.
The stress can deform the top-most aluminum layer and cause cracking in the silicon-dioxide silicon-nitride top dielectric layer. Thermal cycling exacerbates this mechanism. Some methods to minimize this problem include: identifying and using a molding compound with a coefficient of thermal expansion that better matches that of the die, increasing the passivation, or top dielectric, thickness, using a polyimide protective overcoat to absorb the stress, and using narrower aluminum lines that limit the adhesion and stress buildup.
Q: How can I limit the breakdown damage when an oxide is stressed in a power MOSFET device?
A: Use a current limiting resistor or set a lower compliance limit on the SMU. A more active monitoring circuit may be needed if the FN tunneling current is already significant.
(Click on each item for details).
LED Packaging on December 12-13, 2011 in Austin, TX, USA
Copper Wire Bonding Technology and Challenges on December 15-16, 2011 in Malaysia
Semiconductor Reliability on January 17-19, 2012 in San Jose, CA, USA
Wafer Fab Processing on January 17-20, 2012 in San Jose, CA, USA
Introduction to Polymers and FTIR on January 17-18, 2012 in Phoenix, AZ, USA
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