Feature Article - Failure Analysis Procedures, Part 1 - By Christopher Henderson

This article begins a series of five articles on Failure Analysis Procedures. I am often asked about flowcharts for FA. A flowchart describing the process for failure analysis can be useful, especially for individuals new to failure analysis. There are different ways to develop flowcharts for failure analysis. One of the more common methods is to create flows around various electrical failure modes. Here is an example of an FA flow procedure for a static random access memory device, or an IC with a failure in the memory section.

We begin by identifying the type of memory failure. If the failure is a single bit failure or a bit pair failure, one can go straight to the electrical to physical bitmap conversion diagram to physically identify the location of the failing bit or bit pair. If the failure is not a single bit failure, then one should try to identify the row or column involved, or ascertain the pattern involved in the failure. One can then analyze the bitmap or the GDSII file to identify potential points of failure, and mark them for further analysis. This mark is normally placed on the front side of the device, but could be made on the backside, if one decides that a backside approach is preferred. At this point, it can also be useful to look at similar failures for patterns. This can be accomplished by looking a wafer sort data, bitmap data, and inline parametric test data. Once the sample is identified and marked, and other samples identified and marked, we can begin more destructive steps. This involves removing the overlying layers to expose the cells of interest. The metal layers obscure the bits, and our ability to image defective conditions. Once the metal layers are removed and the metal-1 or polysilicon layers are exposed, we can perform passive voltage contrast to help localize and verify the problem row or column metal, or cell/cells. If we find a defect, then we can perform a cross-section of the problem area, or remove the section and analyze it with the higher magnification transmission electron microscope. If we don’t see the defect with passive voltage contrast we can try Atomic Force Probing or SEM nanoprobing to check for leakages. If we are still not seeing a defect, then it makes sense to remove the next layer and look at it with the same tools and techniques. We can continue this process until we locate the defect, or reach the silicon. Once we reach the silicon, we can decorate the substrate with an etch to highlight potential defects.

Is this method foolproof? The answer is "no," but it does provide a worthwhile construct in which to perform an analysis. Again, these constructs can be useful for new analysts, but we need to emphasize that some failures may lie outside the context of this framework. In the next issue, we’ll discuss a failure analysis flowchart for a scan-based failure.