Let’s examine short-channel transistors and halo optimization more closely. In advanced technologies, we want to minimize the diffusion of the dopant atoms. This is especially important with the halo profile. One can improve the halo profile with a flash anneal. This is also important in mixed-signal, digital and RF analog applications. If the halo reaches to the surface, if can alter the effective channel length of the transistor, creating an effect like the reverse short channel effect. As the drain voltage increases, the depletion will spread beyond the surface halo, decreasing the threshold voltage and increasing the saturation drain current. This is similar to a short channel effect, but is instead observed in long channel transistors and degrades the Early voltage.
Another technique used in the lateral asymmetrical channel. This technique, where dopant atoms are implanted at just one fixed angle to form a single halo or pocket, increases the contribution associated with velocity overshoot because of the built-in field at the source end of the transistor. It does improve analog parameters though.
Let’s move on and discuss raised source/drain regions. This technology involves implanting lightly-doped drain regions or extensions to form spacers. The raised portion of the structure is created through selective epitaxial growth on the junction region. One then implants a dopant into this structure and drives it in using rapid thermal anneal. This diagram doesn’t show the salicide layer. This approach drives up the cost of the technology through extra steps, and it is not clear how well this will work for future transistor technologies. However, there are some significant advantages. The implant damage is confined to the epitaxial layer, and it eliminates transient-enhanced diffusion. The junction is formed by driving in the dopants from an elevated location, which helps prevent overdriving. There is also sacrificial silicon for the silicide reaction. It forms a borderless contact, and it reduces the contact aspect ratio.
Stay tuned for the conclusion of this article in November!
In this technical tidbit we’ll discuss some issues and approaches to dealing with high aspect ratio structures like contacts and vias. A problem related to etch is the subsequent deposition step. Deposition is especially challenging with high aspect ratio structures. Conventional Physical Vapor Deposition exhibits problems such as overhang at the top, or re-entrant top corners, thinning on the floor and lower sidewalls, discontinuities at the floor to sidewall corner. As such PVD can no longer meet specifications for many IC structures. An improvement on PVD is physically collimated PVD confines the deposition angle to near zero, which improves film conformity at the door of the structure, but it limits throughput. It is also not appropriate for ultra-thin films.
Yet another approach to PVD is ionized PVD with re-sputter. In this approach one replaces conventional PVD for metal deposition on ICs. The metal atoms are ionized in a plasma and accelerated to surface, producing a directionality. This improves floor coverage, gives a smooth morphology, and results in high-purity films. The added energy can be adjusted to be high enough to re-sputter metal from the floor onto the sidewalls. This yields improved step coverage but can lead to difficulty at the lower corners of a trench. In some of today’s ICs, the aspect ratio exceeds the range of ionized PVD conformity. As a result, many deposition steps are done using Chemical-Vapor Deposition, or CVD. With CVD, one can achieve uniform deposition on all surfaces. However, it can be difficult to control ultra-thin films.
Q: Is oxidation-enhanced diffusion prominent or negligible?
A: The answer depends on the dopant elements involved. Oxidation generates excess silicon self-interstitials, which enhance the diffusivities of atoms that diffuse with a significant interstitialcy component. This includes Boron, Phosphorus, and Arsenic. It retards Antimony, which diffuses primarily by the vacancy mechanism.
(Click on each item for details).
Semiconductor Reliability on January 16-18, 2012 in San Jose, CA, USA
Wafer Fab Processing on January 16-19, 2012 in San Jose, CA, USA
Introduction to Polymers and FTIR on January 17-18, 2012 in Phoenix, AZ, USA
Failure and Yield Analysis on January 23-26, 2012 in Cambridge, United Kingdom
Defect-Based Testing on January 30-31, 2012 in Cambridge, United Kingdom
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