Most semiconductor components are sensitive to overstress. In fact, up to 40% of failed devices returned for analysis are classified as overstress. Since overstress is a mechanism that is so pervasive in the electronics industry, design engineers must consider methods to protect against this problem.
There are five overarching strategies to protect semiconductor devices and integrated circuits from overstress. The first strategy is to limit current through small devices. The most obvious devices that must be protected are input transistors in CMOS circuits. Other transistors that are sensitive are the inputs to differential amplifiers. The second strategy is to ensure that alternate paths exist that can channel the current around sensitive circuits. The most common manifestation of this is the input protection diode. The third strategy is to minimize supply resistance and maximize the capacitance. By minimizing supply resistance, less opportunity exists for the high current discharge creating damaging differential voltages on the chip. By maximizing chip capacitance, the device can absorb more of the discharge with a lower resulting voltage. The fourth strategy is to minimize steps and discontinuities. This helps to prevent regions of field concentration that initiate damage. The final strategy is to identify and minimize parasitic effects. Parasitic transistors, diodes, and resistors can allow voltage and current to couple to sensitive devices that might otherwise be isolated. We’ll take a quick look at a couple of these strategies and some representative circuits below.
This circuit describes a basic approach to protecting a sensitive circuit. The inverter circuit, shown inside the dashed box, contains transistors sensitive to voltage pulses. In a modern circuit, even voltages as low as 5 volts can potentially damage the gates and junctions. To protect the transistors, designers often use input protection diodes and resistors. The resistor shown in the figure will limit the current into the sensitive gate, while the diodes ensure that alternate current paths exist should the voltage on the input go significantly above or below VDD or VSS. In this circuit, the implant-to-well, and the implant-to-substrate diodes in the source regions of the p- and n-channel transistors serve the same purpose for the output; they shunt the current around the transistor should the output go significantly above VDD or below VSS. However, this does require that the transistor junctions be quite large to handle the energy dissipation.
In addition to protecting the input and output pins, the entire power supply network may require some protection for larger pulses that raise the voltage on the entire chip. These circuits are known as clamps. Overstress clamps can be initiated by voltage or frequency triggering. The objective is to not be activated during circuit power up and power down, not to interfere with system functionality, but only activate during the overstress event. Frequency triggered overstress power clamps remain off during dc phenomenon but respond to the ac signal induced by the EOS or ESD pulse event. This is an example of a frequency-triggered clamp. The portion of the circuit outlined in blue is the RC discriminator that determines what range of ac events should trigger the MOSFET clamp on the right end of the circuit.
Voltage triggered overstress power clamps remain off during normal voltage conditions and chip operation, but turn on when a voltage condition is exceeded. This can be an over-voltage condition, overshoot, or undershoot phenomenon or any high current event. This particular structure triggers when the voltage on VDD exceeds the four diode drops, highlighted here in the voltage trigger, and the one in the base-emitter junction of the clamp device, or approximately 3.5 volts total. The bipolar clamp device then turns on, collapsing the VDD rail voltage.
In conclusion, we showed some basic overstress protection circuits. This is an important aspect of the design, as these circuits protect against a common failure mechanism endemic to almost all circuits and applications. There are many different circuit design techniques to protect against these problems. If you are interested in learning more about this topic, we encourage you to consider attending our upcoming course on ESD and Latchup Design and Technology. If you are involved in failure analysis or product engineering, we encourage you to consider our upcoming course on EOS, ESD - Can Failure Analysis Differentiate? You can find more details for both courses on our website.
In recent years, Microelectromechanical Systems (MEMS) have seen rapid growth as companies insert them into various applications. One particularly important technical processing breakthrough that has facilitated the proliferation of MEMS is the Bosch Deep Reactive Ion Etch (DRIE) process. The Bosch DRIE process was developed by scientists working for the etch’s namesake, Robert Bosch GmbH. The Bosch etch is a process that allows precise control of the etch anisotropy by alternating two steps. The first step is the standard isotropic plasma etch using sulfur hexafluoride [SF6]. The second step is the deposition of a Teflon-like passivation layer composed of (C4F8). The next SF6 etch step removes the passivation layer from the bottom of the trench, but leaves the passivation on the sidewalls of the trench. The result is a truly vertical sidewall trench. When one examines the trenches closely in cross section, the sidewalls have a characteristic scalloped profile that is 100-500nm in depth. The Bosch etch can achieve etch rates of several microns per minute.
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EOS, ESD and How to Differentiate on November 7-8, 2012 (Wed.-Thurs.) in San Jose, CA, USA
Introduction to Polymers and FTIR on November 7-8, 2012 (Wed.-Thurs.) in San Jose, CA, USA
Semiconductor Reliability on January 23-25, 2013 (Wed.-Fri.) in San Jose, CA, USA
Failure and Yield Analysis on January 28-31, 2013 (Mon.-Thurs.) in San Jose, CA, USA
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