Feature Article - Substrate Materials Part 3 - By Christopher Henderson

Some companies are beginning to use silicon as an interposer or substrate technology. Silicon has key advantages. One, it is matched to the die in terms of the coefficient of thermal expansion. Two, one can use standard wafer lithography and processing techniques on the interposer. This allows one to use fine geometries. However, the use of a silicon interposer requires a method to connect signals from the front side of the interposer to the backside. This means the use of through silicon vias, or TSVs. The TSV is maturing--but is still a technology that is quite new and untested--so many manufacturers are wary of their use in high reliability applications. This is an example of the Xilinx 2.5D FPGA package structure in cross section. Xilinx uses a silicon interposer with through silicon vias to route signals from one FPGA slice to the other. Notice that they still use a laminate substrate to form the BGA package.

Another substrate material under investigation is silicon dioxide, or glass. The main advantage for glass is that--in addition to the fact that there is a good CTE match to the chip--the dielectric constant is much lower than that of silicon. Silicon dioxide is 3.9, whereas silicon is 11.7. However, glass is not an easy material with which to work. Scientists have demonstrated through glass vias, but haven’t demonstrated manufacturing consistency and high reliability yet. As this technology evolves, this may become a worthwhile alternative to silicon interposers.

Another option engineers are exploring is coreless substrates. In a standard build-up package, there is a core material made from FR4 or BT epoxy laminate as we discussed earlier. A build-up package requires a fan-out region to match the bump and/or the line pitch to the plated through hole pitch. We highlight this region with the yellow ellipses. In a coreless package there is no core material, just build-up materials. This facilitates direct signaling. Designers can use all of the layers for signals, and the approach maximizes wiring efficiency. It also reduces impedance mismatches that occur as the result of the plated-through holes. Co-planarity is also better with a coreless package. The major issue with coreless substrates is warpage. Warpage is up to four times worse with a coreless substrate due to the lack of a rigid core to hold everything in place. As a result, not many manufacturers are using coreless substrates. However, Sony uses this technology in the latest version of their Cell processor family.

The major player for coreless package build-up materials is Ajinomoto. The Ajinomoto Build-up Film--or ABF--is used extensively in the industry already on substrates with cores, and now used for coreless build-up as well. ABF is a three-layer polymer system, with a polyethylene terephthalate (PET) support film, a resin layer, and a cover film. One can deposit copper on the thin to create interconnect traces. Ajinomoto has evolved its ABF to remove the halogens, lower the coefficient of thermal expansion, and allow for narrower vias. It is used widely as a standard build-up material, and is now in limited use for coreless substrates.

This table shows the common materials properties for substrate materials. We show toughened benzocyclobutene (or BCB), Cyclotene (another form of BCB), Polyimide, Epoxy/Phenol (the traditional printed circuit board material), acrylic, and polybenzoxazole (or PBO). Each material has its own advantages and disadvantages. For example, BCB has the best dielectric constant, but suffers from a high coefficient of thermal expansion. Polyimide works well as a high temperature substrate, but suffers from elongation and moisture uptake. Epoxy/phenol is cheap and has a low elongation value, but suffers from a low glass transition temperature. PBO has good tensile strength and a low moisture uptake, but suffers from high elongation and CTE values.