Some companies are beginning to use silicon as an interposer or substrate technology. Silicon has key advantages. One, it is matched to the die in terms of the coefficient of thermal expansion. Two, one can use standard wafer lithography and processing techniques on the interposer. This allows one to use fine geometries. However, the use of a silicon interposer requires a method to connect signals from the front side of the interposer to the backside. This means the use of through silicon vias, or TSVs. The TSV is maturing--but is still a technology that is quite new and untested--so many manufacturers are wary of their use in high reliability applications. This is an example of the Xilinx 2.5D FPGA package structure in cross section. Xilinx uses a silicon interposer with through silicon vias to route signals from one FPGA slice to the other. Notice that they still use a laminate substrate to form the BGA package.
Another substrate material under investigation is silicon dioxide, or glass. The main advantage for glass is that--in addition to the fact that there is a good CTE match to the chip--the dielectric constant is much lower than that of silicon. Silicon dioxide is 3.9, whereas silicon is 11.7. However, glass is not an easy material with which to work. Scientists have demonstrated through glass vias, but haven’t demonstrated manufacturing consistency and high reliability yet. As this technology evolves, this may become a worthwhile alternative to silicon interposers.
Another option engineers are exploring is coreless substrates. In a standard build-up package, there is a core material made from FR4 or BT epoxy laminate as we discussed earlier. A build-up package requires a fan-out region to match the bump and/or the line pitch to the plated through hole pitch. We highlight this region with the yellow ellipses. In a coreless package there is no core material, just build-up materials. This facilitates direct signaling. Designers can use all of the layers for signals, and the approach maximizes wiring efficiency. It also reduces impedance mismatches that occur as the result of the plated-through holes. Co-planarity is also better with a coreless package. The major issue with coreless substrates is warpage. Warpage is up to four times worse with a coreless substrate due to the lack of a rigid core to hold everything in place. As a result, not many manufacturers are using coreless substrates. However, Sony uses this technology in the latest version of their Cell processor family.
The major player for coreless package build-up materials is Ajinomoto. The Ajinomoto Build-up Film--or ABF--is used extensively in the industry already on substrates with cores, and now used for coreless build-up as well. ABF is a three-layer polymer system, with a polyethylene terephthalate (PET) support film, a resin layer, and a cover film. One can deposit copper on the thin to create interconnect traces. Ajinomoto has evolved its ABF to remove the halogens, lower the coefficient of thermal expansion, and allow for narrower vias. It is used widely as a standard build-up material, and is now in limited use for coreless substrates.
This table shows the common materials properties for substrate materials. We show toughened benzocyclobutene (or BCB), Cyclotene (another form of BCB), Polyimide, Epoxy/Phenol (the traditional printed circuit board material), acrylic, and polybenzoxazole (or PBO). Each material has its own advantages and disadvantages. For example, BCB has the best dielectric constant, but suffers from a high coefficient of thermal expansion. Polyimide works well as a high temperature substrate, but suffers from elongation and moisture uptake. Epoxy/phenol is cheap and has a low elongation value, but suffers from a low glass transition temperature. PBO has good tensile strength and a low moisture uptake, but suffers from high elongation and CTE values.
An important concept, both for chip design and Printed Circuit Board (PCB) design is to minimize trace parasitics. Trace parasitics come in the form of resistance, inductance and capacitance. Improving these values helps with signal integrity, precision measurements and power measurements.
An important goal during the design of the board is to minimize resistance. The parasitic resistance of a Integrated Circuit or PCB trace is directly proportional to the length of the trace, and inversely proportional to the height and width of the trace. The equation for resistance in a uniform conductive material with a rectangular cross section is:
where l is the length of the trace, σ is the resistivity of the material, W is the width of the trace, and T is the thickness of the trace material. Test engineers often rout ground signals as planes rather than traces because planes offer low impedance.
Inductance is another important consideration during the design of a board or IC. Minimizing inductance is important for switching high currents and testing high bandwidth amplifiers. The inductance of a trace depends on the shape and size of the trace, as well as the geometry of the signal path through which the currents flow to and from the load impedance. The equation for inductance is
where D is the distance between traces, W is the width of the trace, µo is the permeability of air, and µr is the relative permeability of the medium (the dielectric material in this case). We can minimize trace Inductance in the following ways:
Capacitance is still another important trace parasitic that we need to minimize. The equation for capacitance is
where W is the width of the trace, D is the distance between traces, ε0 is the dielectric constant of air, and εr is the relative dielectric constant (or permittivity) of the medium (the insulating material in the board). The value of εr depends on the PCB insulator material. FR4 fiberglass has a relative permittivity of about 4.5, while teflon, by contrast, has a relative permittivity of about 2.7. Therefore, teflon is superior for high frequency applications, since it leads to lower values of parasitic . capacitance. Another design practice that can reduce capacitance is to add a GND plane between traces removes trace-to-trace capacitance and reduces crosstalk. SiO2 has a relative permittivity of about 3.9, so newer chips use Low-K dielectrics where the relative permittivity might be between 2.0 and 3.0.
Q: What are Base and Metal Layers?
A: Base layers are the layers which are implemented in the silicon substrate (like source/drain implants, VT implants, NWELL layer, etc.). Metal layers obviously refer to the mask layers associated with the back end of the process (like M1, M2, M1-M2 via, etc). In the EDA process process flow base layers are taped out first and then metal layers.
Please visit http://www.semitracks.com/courses/analysis/failure-and-yield-analysis.php to learn more about this exciting course!
(Click on each item for details).
Semiconductor Reliability on January 11-13, 2016 (Mon.-Wed.) in San Jose, CA, USA
Failure and Yield Analysis on January 18-21, 2016 (Mon.-Thurs.) in San Jose, CA, USA
Failure and Yield Analysis on May 17-20, 2016 (Tues.-Fri.) in Munich, Germany
EOS, ESD and How to Differentiate on May 23-24, 2016 (Mon.-Tues.) in Munich, Germany
Semiconductor Reliability and Product Qualification on May 30-June 2, 2016 (Mon.-Thurs.) in Munich, Germany
If you have a suggestion or a comment regarding our courses, online training, discussion forums, reference materials, or if you wish to suggest a new course or location, please feel free to call us at 1-505-858-0454, or e-mail us at firstname.lastname@example.org.
To submit questions to the Q&A section, inquire about an article, or suggest a topic you would like to see covered in the next newsletter, please contact Jeremy Henderson by e-mail (email@example.com).
We are always looking for ways to enhance our courses and educational materials.
Home > Newsletters > 2015 October Newsletter