This short section will discuss a historical technique for metal deposition known as evaporation. We present this topic mainly for completeness, although some experimental processes might utilize this method of deposition even today.
Evaporation was the earliest method for depositing metal conductors on semiconductor devices. Evaporation is a highly directional process; the evaporated atoms travel in a straight line to the wafer surface. This can lead to problems such as step coverage. Evaporation also produces small grain sizes. This is a concern with regard to both stress induced voiding and electromigration. Atom movement occurs more readily along grain boundaries; therefore, the smaller the grain sizes, the more grain boundaries are present, and greater the potential for atom movement, which is the physical process associated with electromigration and stress voiding.
There are two types of evaporation systems used in semiconductor applications: the filament evaporation system and the electron beam evaporation system (Figure 1). In a filament-based evaporation system, the filament is heated to boil off the material. The evaporated material will coat the wafers, and everything else inside the chamber. In an electron beam evaporation system, an electron beam gun accelerates electrons toward the evaporation target. The electrons impart energy to the target in the form of heat. As the target heats up, the material is evaporated. Like the filament evaporation system, the material will deposit on the wafers and everything else in the chamber.
Deposition in an evaporation system is heavily dependent on the angle of deposition (Figure 2). Since the atoms that comprise the thin film travel in a straight line, the deposition rate is a function of the cosine of the angle. The larger the angle, the slower the deposition process will be. For this reason, most evaporation systems are constructed such that each wafer is perpendicular to the target.
Evaporation systems suffer from several different problems. First, the deposition rate and film thickness cannot be precisely controlled. As we discussed earlier, the cosine law means that one cannot achieve a uniform thickness. Second, evaporation is not a suitable method for depositing compounds. Most aluminum metal systems have a few percent copper added to increase resistance to electromigration. Third, step coverage can be rather poor due to the line of sight path that the atoms travel. Some systems alleviate this problem by moving and rotating the wafers during the evaporation process; however, this increases the mechanical complexity of the system and decreases its reliability. Finally, one can damage the wafers from radiation associated with the electron gun. The high accelerating voltage can cause threshold voltages to shift on sensitive MOS devices.
The scanning electron microscope image in Figure 3 shows an example of evaporated metal. We removed the overlying dielectric with a wet chemical etch to help delineate the grain boundaries. Note that the grains are quite small. Also note that there are significant gaps in the grain boundaries in this segment of metal. This is caused by a failure mechanism known as stress induced voiding, or stress migration. This phenomenon is more common in evaporated metal, since the smaller grains provide numerous grain boundaries through which the aluminum atoms can migrate. This is another disadvantage of evaporated metal: it suffers from reliability issues. As such, the semiconductor industry has mostly moved away from this deposition.
In conclusion, we discussed evaporation. This is a technique for depositing some metal layers on semiconductors. Historically, the semiconductor industry used evaporation to deposit aluminum interconnects during the 1970s and 1980s. Metal evaporation suffers some several deposition and reliability problems, including step coverage, thickness control, and stress voiding or stress migration. As such it is no longer in general use in the semiconductor industry. A few research projects use evaporation as a technique to deposit conductors. For example, some compound semiconductor research efforts might use evaporation to put down gold or other metals. However, we are unlikely to see a resurgence in this technique.
There is a not-so-widely known theorem in statistics called Chauvenet’s theorem that we use in the semiconductor industry to identify outliers. Although it is not widely known, it forms the underlying basis of the more widely used criteria for Statistical Yield Limits (SYL) and Statistical Bin Limits (SBL).
The basic problem to solve is how to identify an outlier data point from a set of data. The point could be part of the distribution, or it may be outside of it. We need a formalized way to discern this, rather than trying to "eyeball" the value on a histogram or other plot, or some other form of guessing. The concept behind Chauvenet’s theorem is to treat the data set as following a normal distribution with each data point consisting of a value Z, where Z is the distance in standard deviation units (sigma) from the mean (mu). X represents the actual data value. Once we know this, we can apply Chauvenet’s criteria: If the expected number of measurements at least as bad as the suspect measurement is less than 1/2, then the suspect measurement should be rejected. This can be written as the term 1-(1/2)n, where n is the number of samples.
Chauvenet’s criteria can be graphed as a plot of standard deviation units as a function of the number of samples. Notice that one requires about 300 samples to determine if an outlier is outside of 3 standard deviation units.
A particular application of this theorem sometimes goes by the name 3 Sigma Distribution. It is commonly used in the semiconductor industry to identify outliers during wafer probe testing. The 300 wafer number allows the engineer to detect wafers or wafer lots that lie outside of the 3 sigma limits for tests like Statistical Yield Limit (SYL) or Statistical Bin Limit (SBL).
Q: Is there a maximum fluorine level allowed for bondpads?
A: There is an unofficial spec limit of 6 atomic percent using Auger Electron Spectroscopy that has been in use since the early 1980s (J.F. Gives et.al., Proc ECC 1982, pp.266) (J. Nesheim et.al., ISHM 1984, pp. 70-78) (J. Pavio et.al., ISHM 1984, pp. 428-432)
One can also use EDX and XPS as ways to check for fluorine, but you need to remember that the interaction volumes are different, and so the results would be different depending on the analytical tool.
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Failure and Yield Analysis on January 30-February 2, 2017 (Mon.-Thurs.) in Portland, OR, USA
Advanced CMOS/FinFET Fabrication on February 7, 2017 (Tues.) in Portland, OR, USA
Semiconductor Statistics on February 8-9, 2017 (Wed.-Thurs.) in Portland, OR, USA
Defect-Based Testing on May 3-4, 2017 (Wed.-Thurs.) in Munich, Germany
Failure and Yield Analysis on May 8-11, 2017 (Mon.-Thurs.) in Munich, Germany
Semiconductor Reliability and Product Qualification on May 15-18, 2017 (Mon.-Thurs.) in Munich, Germany
Semiconductor Statistics on May 22-23, 2017 (Mon.-Tues.) in Munich, Germany
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