Non-volatile memory, which can hold data with power removed, has become critical to devices like PDAs, cell phones, and digital cameras. Over the next several issues, this three-part article series will discuss basic non- volatile memory technologies to give you a better understanding of their background and importance.
In Part 1, we will cover one of the original non-volatile memory technologies, the metal nitride oxide silicon, or MNOS technology. Part 2 will discuss an improvement over MNOS called silicon oxide nitride oxide silicon (SONOS) technology, and its predecessor, silicon nitride oxide silicon (SNOS). Next, we’ll discuss the floating gate avalanche injection MOS or FAMOS transistor, used extensively for years in ultraviolet erasable memory. One of the more popular variants of this technology is flash memory. Part 3 will cover the strengths and weaknesses of NAND and NOR, the two most common non-volatile memories in use today.
Two basic mechanisms store charge in non- volatile memory. The first method, which forms the basis for MNOS technology, utilizes traps in the insulator or at an interface. The second method, called floating gate technology, stores the charge on a conductive or insulator material sandwiched in between the control gate and the silicon channel.
In 1967, Richard Wegener and his colleagues at the Sperry Rand Research Center developed the metal nitride oxide silicon transistor (MNOS) while researching technologies to help store data and reduce power dissipation in military electronics. When they replaced the oxide layer in a standard MOS transistor with a nitride-oxide stacked layer, the bonds between the nitride and the oxide created an interface containing a high level of traps (unterminated bonds that attract positive or negative charge). Placing a high voltage on the gate forced charge onto these interface traps, while placing a high voltage of the opposite polarity on the gate removed the interface traps. One disadvantage of this technique is that trapped charge tends to disperse or recombine, limiting the storage time of the structure. The higher the storage temperature, the more quickly the charge recombines. Researchers have been able to improve the retention time by replacing the top metal gate with a silicon gate.
The figure on the left illustrates the basic MNOS cell structure and a graph of the structure’s charging and discharging times. The graph shows an example set of curves for a combined dielectric stack of 1000 angstroms and differing oxide thicknesses. For thinner oxides, the charging and discharging times decrease substantially. However, a MNOS structure requires a long charging time to retain trapped charge. Conversely, a short charging time leads to a short discharge time. Because of this problem, MNOS memory never became popular as a high-volume commercial technology. However, its greater tolerance of radiation made the MNOS suited for some niche applications, such as military and space.
Wafer level bakes have gained in importance in recent years for several reasons. Like wafer level testing, wafer level bakes can be performed prior to packaging, allowing engineers to send results to process engineers more rapidly. Wafer level bakes are primarily used to study temperature-only driven mechanisms, charge retention in non-volatile memories, and mechanisms like gate sinking in pHEMTs (High Electron Mobility Transistors). Another advantage of the wafer level bake is that one can stress components at higher temperatures than normally possible in packaged devices. Wafer level bakes are typically performed at 250-275°C. This is particularly useful for memory retention tests, since most devices are specified to work for 10 years or longer. A higher temperature stress allows the engineer to compress the stress test into a shorter time period.
Wafer level bakes have been used for some time. They started in the mid-1980s as engineers began to study charge retention in EEPROMs. David Baglee et. al. mention wafer level bakes in their 1990 paper on EPROM reliability.1 Prior to this, many engineers performed bakes on packaged components to study this problem as well as other oxide reliability problems. Wafer level bakes are not typically used for standard reliability testing on logic devices, since the better model for thicker oxides (>50Å) is the Eyring model (a model that includes both voltage and temperature), or the Power Law model (a model that is sometimes used for ultra-thin oxides, or those less than 50Å).
1 David A. Baglee, Lynn Nannemann, and Cheng Huang, "Building Reliability into EPROMs," Proc. Int. Reliab. Phys. Symp., 1990, pp. 12-18.
Q: Where can I find some current papers on NTBI? --Joey
A: Joey, the best place to find information on the NBTI mechanism is in the Proceedings of the International Reliability Physics Symposium. The most important papers can be found in the last 6-7 years of proceedings, as it has become a major issue in recent years. We also have a good summary with reference to key papers in our Online Training system, http://www.semitracks.com/online-training/, if you're interested. Best regards, Chris
Please visit http://www.semitracks.com/courses/photovoltaics/photovoltaics-overview.php to learn more about this exciting course!
(Click on each item for details).
Failure and Yield Analysis on September 8-11, 2009 in Munich, Germany
Semiconductor Reliability on September 14-16, 2009 in Munich, Germany
MEMS Technology on October 5-6, 2009 in Austin, TX, USA
Photovoltaics Overview on October 7, 2009 in Austin, TX, USA
Photovoltaics Technology and Manufacturing on October 8, 2009 in Austin, TX, USA
Wafer Fab Processing on October 19-22, 2009 in Enschede, Netherlands
Photovoltaics Technology and Manufacturing on October 30, 2009 in Anaheim, CA, USA
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