Historically, failure analysts used either mechanical or chemical means to decapsulate integrated circuits. They used primarily mechanical means on hermetically-sealed components (ceramic and metal packages) and primarily chemical means on plastic encapsulated microcircuits. The advent of newer bonding materials like copper wire creates problems for traditional methods though. Chemical decapsulation can damage copper wires. While engineers work on new solutions and procedures for chemical decapsulation in these devices, other companies developed alternate methods for decapsulation. The most important of these new tools is the laser decapsulation system.
Laser decapsulation uses the energy from a laser beam to remove the mold compound from plastic encapsulated microcircuits. Scientists developed three different laser systems for this purpose: Pulsed CO2, Nd-YAG, and KrF Excimer laser systems.
One can remove mold compound epoxies with pulsed CO2 systems that operate at 10.6µm wavelengths. This wavelength is an infrared energy source. As such, the epoxy absorbs the energy from the laser, causing the epoxy in the mold compound to melt and eventually vaporize. However, this wavelength damages the die surface. The passivation layers absorb this energy and couple it into the interconnect below, creating damage and rendering circuits non-functional.
One can remove mold compound epoxies with pulsed neodymium: yttrium-aluminum-garnet (Nd:YAG) lasers operating at 532nm. At this wavelength, the dark-colored epoxy also absorbs the energy, causing it to melt and then vaporize. However, this wavelength also damages the die. At 532nm, the laser energy passes through the dielectric, but is partially absorbed by the metal layers below. In fact, this wavelength can be used in laser cutting systems that cut metal lines. Again, this leads to damage to the interconnect, rendering circuits non-functional.
One can also remove mold compound epoxies with a pulsed krypton-fluoride (KrF) excimer laser than operates at 248nm. At this wavelength, the energy is deposited very close to the surface of the epoxy. This leads to an ablative removal method. This wavelength also induces less damage to the die surface, as the top passivation absorbs more of the energy from the laser. Although this does less damage, it will still render sensitive circuits non-functional. This laser wavelength is also slower than the other wavelengths.
It is important to control the pulse repetition rate. If one uses too high of a pulse repetition rate or too long of a pulse width, this action can result in the epoxy polymerizing and not being removed. Also, the laser removes the epoxy in the mold compound, but not the silica particles. To remove the silica particles, one needs airflow to blow them away from the active cutting surface. Since the laser decapsulation process will render most circuits non-functional, one must stop the cutting process just short of the die surface. To keep the circuit functional, one must use plasma cleaning or a chemical decapsulation for the final remaining material.
Figures 1 and 2 show a low magnification and a high magnification image of a chip that has been decapsulated using the laser decapsulation method.
Several companies manufacture laser decapsulation systems. Both Controlled Laser Corporation and Digit Concept make these systems. Digit Concept also licenses some technology from Controlled Laser Corporation to make several tools. We show an example of a system from Controlled Laser Corporation below (Figure 3).
As packages become more complex and the materials change, the use of laser decapsulation is likely to grow. Laser decapsulation does allow for more precision in the x- and y-directions, as well as reasonable control in the z-dimension. The big drawback to laser decapsulation is damage to the chip, which can render it non-operational. As scientists study this problem and develop new laser techniques, the impact on functional circuits should go down. Look for more development in this area in the future.
The general concepts for Highly Accelerated Stress Testing (HAST) are straightforward to understand. The idea is to stress devices at temperatures between 110-130°C for JEDEC tests, and possibly as high as 156°C for device characterization. The relative humidity level should be maintained at 85% for this testing. However, during warm-up and cool-down, the thermal load from the devices and boards can affect this behavior. For example, incorrect airflow can lead to condensation on the components, as they warm more slowly than the environment. In order to avoid this problem, the wet-bulb temperature needs to remain below that of the electronics. These graphs show a full-load ramp-up to 156 degrees centigrade, 85% relative humidity. The top graph shows an example before optimization of the fan behavior, and the bottom graph shows it after optimization. After optimization, the wet-bulb temperature is always below the temperature at any point during the cycle.
There can be a different set of problems during the cool-down period. For instance, the mechanical pressure relief must be slow, on the order of 3 hours, to allow for the units to cool correctly without resulting in pressure issues. One should not vent the system until the pressure reaches 1 atmosphere. Also, one must hold the relative humidity at the test value to ensure correct results as the units must retain the moisture they acquired during the test.
This can require some experimentation, so engineers should plan time in the schedule to characterize this behavior should they begin performing HAST testing, if they begin using new equipment, or even if they design new boards to stress new components.
Q: I hear a lot of discussion about NBTI (Negative Bias Temperature Instability). Is PBTI (Positive Temperature Instability) a problem as well??
A: It can be in High-K Metal Gate technologies, but it is not a big issue in circuits with oxide or oxynitride-based gate dielectrics. Mikael Denais and a team from ST Microelectronics did a nice study on this issue back in 2004, and determined that while PMOS NBTI can lead to changes in threshold voltages of as much as 8%, NMOS PBTI, NMOS NBTI, and PMOS PBTI normally exhibit changes of less than 1%. Researchers do see bigger shifts in PBTI with High-K Metal Gate transistors, and they are actively studying this phenomenon.
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