Semitracks Blog

December 8, 2011


Just finished up the 2011 IEEE International Electron Devices Meeting. Can't wait for next year's!

 

December 1, 2011


Technical Tidbit

Thermomechanical stress in components can lead to some interesting failure mechanisms. An example of this is a mechanism called aluminum sliding. This was first reported in the early 1990s by Intel, but more recently, some companies have experienced a resurgence in this problem.

The stress can deform the top-most aluminum layer and cause cracking in the silicon-dioxide silicon-nitride top dielectric layer. This mechanism is exacerbated by thermal cycling. Some methods to minimize this problem include: identifying and using a molding compound with a coefficient of thermal expansion that better matches that of the die, increasing the passivation, or top dielectric, thickness, using a polyimide protective overcoat to absorb the stress, and using narrower aluminum lines that limit the adhesion and stress buildup.



November 17, 2011


Ask the Experts

Q: Is oxidation-enhanced diffusion prominent or negligible? A: The answer depends on the dopant elements involved. Oxidation generates excess silicon self-interstitials, which enhance the diffusivities of atoms that diffuse with a significant interstitialcy component. This includes Boron, Phosphorus, and Arsenic. It retards Antimony, which diffuses primarily by the vacancy mechanism.

 

November 3, 2011


In this technical tidbit we’ll discuss some issues and approaches to dealing with high aspect ratio structures like contacts and vias. A problem related to etch is the subsequent deposition step. Deposition is especially challenging with high aspect ratio structures. *Conventional Physical Vapor Deposition exhibits problems such as overhang at the top, or re-entrant top corners, thinning on the floor and lower sidewalls, discontinuities at the floor to sidewall corner. As such PVD can no longer meet specifications for many IC structures. *An improvement on PVD is physically collimated PVD confines the deposition angle to near zero, which improves film conformality at the floor of the structure, but it limits through-put. It is also not appropriate for ultra-thin films.
Yet another approach to PVD is ionized PVD with re-sputter. In this approach one replaces conventional PVD for metal deposition on ICs. The metal atoms are ionized in a plasma and accelerated to surface, producing a directionality. This improves floor coverage, gives a smooth morphology, and results in high-purity films. The added energy can be adjusted to be high enough to re-sputter metal from the floor onto the sidewalls. This yields improved step coverage but can lead to difficulty at the lower corners of a trench. In some of today’s ICs, the aspect ratio exceeds the range of ionized PVD conformality. *As a result, many deposition steps are done using Chemical-Vapor Deposition, or CVD. With CVD, one can achieve uniform deposition on all surfaces. However, it can be difficult to control ultra-thin films.

October 27, 2011


Ask The Experts

Q: Is oxidation-enhanced diffusion prominent or negligible? A: The answer depends on the dopant elements involved. Oxidation generates excess silicon self-interstitials, which enhance the diffusivities of atoms that diffuse with a significant interstitialcy component. This includes Boron, Phosphorus, and Arsenic. It retards Antimony, which diffuses primarily by the vacancy mechanism.

October 15, 2011


Technical Tidbit

Sometimes, analysts ask whether they should purchase a Cold Cathode or a Schottky cathode field emission SEM. Although the Cold Cathode and Schottky cathode field emission systems both have excellent resolution, there are some differences between the two configurations. The Cold Cathode performance is achieved through a sharp tungsten tip. The sharp tip leads to a very high brightness, which in turn leads to higher resolution at low accelerating voltages. Cold Cathode Field Emission gives best images, but these sources are sensitive to gas atoms in the chamber, so vacuum must be better, which increases cost of system. The current can be unstable, so Cold Cathode Field Emission doesn't work well for certain applications like energy dispersive x-ray analysis. The low energy spread reduces chromatic aberration, leading to the highest quality images. The Schottky field emission uses thermal assistance. This reduces performance slightly but gives a more stable beam, making it a better choice for applications that require higher current. Some Schottky emitters use zirconium oxide coated tips to reduce the energy barrier at higher temperatures. Notice the lower probe diameter at higher beam currents for the Schottky emission configuration.

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October 1, 2011


Technical Tidbit

Sometimes the floor environment is different than the standard values given of 30°C/60%RH. One must understand how to calculate the correct floor life. Let's work through that calculation for parts that pass MSL 4. The packages have a thickness of <2.1mm, and they will be placed in an environment at 30°C/90%RH.

Example: Parts pass in MSL 4. Floor life in pkg with thickness <2.1mm, under environment 30°C/90%RH, floor life is 0.5 day.

If you look in J-STD-033B in Table 7.1 (Page 21), you should be able to find this part of the figure (bottom part of table). Locate MSL 4 (Level 4), go over to the 90% RH column and locate the row for 30°C. The value reads 1 day, so the recommended total equivalent floor life is 1 day. If you have specified a floor life of 0.5 days, you are within the specification called out by JEDEC J-STD-033B.

September 15, 2011


Ask the ExpertsAsk the Experts

Q: I need the actual info on: MSL 2 sample (Rel stress soaking: 85 °C/60%RH, 168hrs). Floor life is 1 year under 30 °C/60%RH storage. What is the floor life if storage under 30°C/70%RH?

A: The best way to make this calculation is to use Peck's Formula to calculate an acceleration factor.

The AF (ratio of TF values, 70%RH/60%RH) = (RH70%/RH60%)-a * exp([Ea /k](1/ T70% -1/ T60%])

The temperatures are the same between the two, so only the humidity is a factor. We'll use 2.7 for a (the humidity exponent) – a typical value for this calculation.

AF (70%/60%) = (70/60) 2.7
AF (70%/60%) = 1.516

So the floor life storage would be 1 year / 1.516 or 0.6595 years (7.914 months) at 70%RH.

August 31, 2011


Ask the ExpertsAsk the Experts

Q: We are using the growth equation (see Excel GROWTH function for details) to model degradation in InGaN laser diodes. Is this approach acceptable for prediction purposes?

A: Using the GROWTH function in Excel presumes that the degradation process will be slow and non- catastrophic. While this approach might be acceptable on a mature process line where no catastrophic degradation occurs, it is quite dangerous to make this assumption across all device types or technologies. Some devices can degrade gradually for a period of time and then exhibit a dramatic, or catastrophic decrease in output.

August 9, 2011


Look for a further push out on 450mm wafer adoption. Investment dollars for this transition won't be there.

July 20, 2011


Experts at Semicon West predicted that economics, not technology, would slow the introduction of EULV and 450mm even further. Read more about this here!

July 14, 2011


Ask the ExpertsAsk the Experts

Q: I am looking at determining Tj for some of our LEDs to understand the effect of droop on light output performance. I am looking to get a handle on the typical thermal resistance (theta-JA) that this package would exhibit. The chip is flip-chip mounted onto a small PCB evaluation board. The die size is just over one square millimeter. I just need a back of the envelope value for small flip-chip package theta-JA (sill air). Does JEDEC give any guidance or do you know off the top of your head what value range would be?

A: I would need some additional details to figure out what theta-JA would be. Specifically, we would need to know what package you're planning to use. Here is a rough figure. For a 1 millimeter-thick package, like a TSSOP, the theta-JA value is approximately 80C/Watt. JEDEC talks mainly about how to measure these values (IR thermography, etc. - JEP110 is a good source here). There are a number of documents associated with JESD-51 (the main standard for thermal resistance) that can help in this determination as well. I would try to make a measurement to really determine what you're dealing with, if possible.

July 1, 2011


Capacitance-Voltage Plotting – Part 1
By Christopher Henderson

Capacitance-voltage or CV plotting, is a common electrical technique for investigating charge phenomena in MOS structures and transistors. In this article, we'll review some of the characteristics of the CV plot, and how it is used to identify and characterize yield and process integration problems.

Figure 1 shows a high and low-frequency capacitance-voltage plot of an ideal MOS structure. The solid line denotes the high frequency curve, while the dashed line denotes the low frequency curve. The capacitance is high when the structure is in accumulation, decreases toward the flatband condition at zero volts applied to the structure, and decreases further toward Cmin, the steady state high frequency condition. In the low frequency condition, the capacitance begins to rise again at a voltage called the match point. As the voltage increases, the capacitance increases to a level similar to that in accumulation. This is sometimes referred to as a quasi-static CV measurement, and is measured using the voltage ramp method. In the voltage ramp method, the voltage is ramped very slowly at a given rate, typically less than 50 mV/sec. The measured displacement current is proportional to the capacitance. The frequency is considered to be low when the generation of electron-hole pairs keeps up with the signal. When the frequency is high, only majority carriers can follow the signal. At low frequencies, the charge exchange with the inversion minority carriers is in step with the varying signal. The small signal response dQ to dV appears at the surface (inversion) rather that at the depletion boundary. As the inversion layer forms, the capacitance increases back to Cmax ! Cox.

Fig. 1. High and Low Frequency Capacitance- Voltage plot of an ideal MOS structure.

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Figure 2 shows a high-frequency capacitance-voltage, or CV plot of an ideal MOS structure. High frequency measurements allow the user to hide the effects of minority carriers since minority carriers cannot react fast enough to follow the signal. The capacitance is high, approximately that of the ideal capacitance across the oxide, when the voltage is negative. When the voltage is negative, the MOS structure is in accumulation, so the surface hole concentration increases, raising the capacitance. At flatband, the capacitance should be equal to the ideal capacitance for the flatband condition. As the voltage goes positive, the MOS structure goes into depletion. The surface electron concentration increases, but remains at a level too low to offset the decrease in surface hole concentration. In weak inversion, the surface electron hole concentration is higher than the surface hole concentration, but the depletion width increases, lowering the capacitance further. In strong inversion, the surface electron concentration equals the surface hole concentration at flatband, and the depletion width reaches its maximum. The capacitance reaches it's minimum at this value as well. This is also the threshold voltage point, where "s is approximately equal to 2#b. The steady-state condition is reached when sufficient electrons are supplied to the surface mechanisms like electron-hole pair generation.

image002

June 15, 2011


Technical Tidbit

There is currently a lot of research and development work on Through-Silicon Vias or TSVs. Although polysilicon in the TSV makes for a good material from the standpoint of a good thermal match, manufacturers would prefer to cause copper, since it has a much lower resistance. Copper has a much higher coefficient of thermal expansion than silicon, leading to several failure mechanisms. A common failure mechanism is a phenomenon called copper pumping. During thermal cycling, the copper expands and contracts, alternately pressing up on the back end of the line (BEOL) materials, and relaxing back. This creates the bulge seen in this image. This pumping action causes stress in the BEOL layers, leading to BEOL damage, or cracking in the metal and dielectric layers. Most process engineers work to reduce the copper pumping effect through the use of annealing and sintering. These steps increase grain size and reduce the coefficient of thermal expansion somewhat.

image001

June 8, 2011


Ask the ExpertsAsk the Experts

Q: How can I limit the breakdown damage when an oxide is stressed in a Power MOSFET device?

A: Use a current limiting resistor or set a lower compliance limit on the SMU. A more active monitoring circuit may be needed if the FN tunneling current is already significant.

To post, read, or answer a question, visit our forums. We look forward to hearing from you!

May 22, 2011


Course Spotlight

EOS in Manufacturing Webinar

Electrical Overstress (EOS) and Electrostatic Discharge (ESD) account for most of the electrical failures of devices that occur in factories and in the field.. The effects of ESD on integrated circuits have received much attention in technical literature, standards bodies and educational workshops and tutorials. The problem has been approached in a systematic manner which has resulted in relatively successful practices for design of robust devices and control procedures for the factory. However, the same cannot be said for the effects of the broader categories of electrical stresses generally referred to as electrical overstress (EOS). This disparity is reflected in the typical Pareto analysis

of failures in electrical assembly where EOS is often the most commonly assigned cause of failure and may exceed the incidence of ESD by 10 times or more. One of the main reasons for this is that EOS sources are widely varied and very application dependent. As a result, no simple broad models for EOS have emerged comparable to HBM and CDM for ESD. Common device design practices have not been developed to the same extent, system level approaches tend to be ad hoc and responsibility for controlling potential sources in manufacturing tends to be diffused or non-existent.

Learn more at: http://www.semitracks.com/index.php/en/courses/public-courses/analysis/eos-in-manufacturing