2005 November Newsletter

Volume 1, Issue 7

November 2005

Welcome to the Semitracks Online Monthly Newsletter! It is our goal that you find this newsletter interesting, informative and useful. Please email any comments or feedback to This email address is being protected from spambots. You need JavaScript enabled to view it. .

1. Process Integration Course

Presenter - Dr. Badih El-Kareh

December 6-8 at the Embassy Suites - Santa Clara, CA

Semitracks, along with Semiconductor International, have put together a three-day course on Semiconductor Process Integration for CMOS, Analog, and Mixed Signal Technologies. Dr. Badih El-Kareh of Texas Instruments will give an overview of the process integration challenges associated with today's advanced semiconductor devices. Dr. El-Kareh will cover passive and active components, contact and interconnect issues, isolation technologies such as STI and SOI, transistor integration issues, as well as full CMOS, BiCMOS and high speed bipolar process integration techniques. The course will be held at the Embassy Suites in Santa Clara, California, from Tuesday, December 6 through Thursday December 8. The course will run from 8 AM to 5 PM with an hour lunch break each day. To register for this event, click here.

2. Upcoming Conferences

International Reliability Physics Symposium

March 26-30, 2006 San Jose McEnery Convention Center in San Jose, CA

To view the IRPS website, click here.

Semicon West 2006

July 10-14, 2006 Moscone Center in San Francisco, CA

For more information, click here.

3. Course Schedule

Invest in yourself and your staff. Time is running short to enroll in our Winter courses on Thermal Management, Packing Technology, Packaging Design, and ESD. Come and learn from the experts!

Thermal Management

As new, more powerful chip designs are introduced, they consume more power. This has made thermal management an important concern in today's high performance systems. Systems ranging from active electronically scanned radar arrays to web servers require components that can dissipate heat efficiently.

Thermal Management (January 20, 2006) - Scottsdale, AZ

Packaging Technology

This course will provide an overview of the current business climate, anticipated trends and the associated impact on assembly/packaging roadmaps. There will be an in depth discussion of both high-end CPU roadmaps plus the roadmaps to address the multitude of communications and network devices that are driving the digital revolution. The course will generically address typical assembly flows and cost implications for both wafer fabrication and assembly with special focus on what the low cost alternatives will be in both camps

Packaging Technology (January 23-24, 2006) - Scottsdale, AZ

Packaging Design

This course provides an overview of the packaging design process. The course covers current packaging technologies, including chip scale packaging, Ball Grid Array technology and other current concepts. This class focuses on techniques and the importance of thermal and mechanical simulations. Discussions and examples will concentrate on thermal performance simulations, assembly & packaging stresses, package reliability (including solder joint fatigue simulation), and interactions between chip and package. In addition, a special section will be examples of successful wafer level simulations.

Packaging Design (January 25-27) - Scottsdale, AZ

ESD Tech Course

Electrostatic Discharge (ESD) and Latchup are a critical concern for the semiconductor and electronics industry. Both ESD and Latchup account for more than $4 Billion in losses each year. This problem is likely to grow in the future as smaller feature sizes are susceptible to damage at lower static voltages and latchup under more subtle conditions.

In this course, the fundamentals of latchup to modern latchup issues will be discussed. The curriculum will include latchup physics, test structures, characterization, process and technology issues, and new latchup issues in the industry today. The topic will then change to fundamentals of ESD. The instructor will first give a background tutorial on ESD physics, electro-thermal and statistical models. The course will then cover CMOS, silicon on insulator (SOI) and silicon germanium (SiGe) technologies. The course is also cover ESD devices, circuits, and process issues in RF CMOS, RF BiCMOS silicon germanium technologies, and gallium arsenide (GaAs).

ESD Tech (January 18-19, 2006) - Scottsdale, AZ

Failure and Yield Analysis

Are you new to failure analysis? Does your position require you to have an understanding of failure analysis? Learn about the latest techniques for analyzing complex devices. We have the most comprehensive short course in the industry covering failure analysis. We cover all the techniques from the simple ones (such as Liquid Crystal) all the way to complex ones (such as PICA and Laser Voltage Probing). Learn the secrets of analyzing a component right every time.

Failure and Yield Analysis (April 24-27, 2006) – Austin, TX

Failure and Yield Analysis (May 15-18, 2006) – Munich, Germany

Reliability

Reliability is a critical element to the success of any semiconductor product. Reliability margins are increasingly squeezed by today’s deep submicron technologies. Learn about the major reliability failure mechanisms, test structures, and test equipment. Learn how to optimize reliability, performance, and cost.

Semiconductor Reliability (May 10-12, 2006) – Munich, Germany

Process Integration

Process Integration is becoming more challenging with each technology node. The fortunes of your company may depend on how successfully you and your team can integrate disparate processing steps into a single, optimized flow. Lily Springer, our expert in Process Integration and Mixed Signal Design, guides you through the critical and challenging aspects of this topic. She covers both digital and analog issues related to process integration. Let your colleagues know!!

Semiconductor Process Integration (December 6-8) – Embassy Suites - Santa Clara, California

To register for our courses, register online or download the registration form. Fax completed form to Semitracks at (505) 858-9813, or call (505) 858-0454 to register by phone.

We offer other courses as well as in-house courses. For more information, visit our website at http://www.semitracks.com.

4. Semitracks Segment of the Month

Semitracks’ new and improved online training is convenient, up-to-date, and cost effective. Access the same material presented in our courses whenever you need it, right when you need it without having to worry about the high costs and hassle of traveling. The semiconductor field is an ever-changing one. With access to the most current information, you can stay on top of the new technology. Online training is also very cost effective. For only $500 per year, you gain access to thousands of dollars worth of courses and course material.

Give our online training a try – for free. This month’s topic is an overview of Thermal Degradation. Thermal Degradation is a continuing concern in today's semiconductor components. This includes intermetallic formation and lead degradation. To learn more, click here.

Sign up to access all of Semitracks online training at http://www.semitracks.com/default.htm and “Learn from the Experts” when it’s convenient for you.

5. Technical Tidbits

The Value of Circuit Editing

This flowchart helps to illustrate the value of the FIB. When the IC design house starts a design, they first create the design, then lay it out, perform extensive verification. If the design verifies and simulates correctly, masks are then generated and the design is fabricated. After fabrication, the silicon devices are tested. If the circuit is working, full production can begin, followed by packaging, assembly, system test and debug. If the circuit is not working, it must be debugged. This occurs using a combination of test techniques, electron beam probing, and optical beam probing. Once the fix is identified it can be implemented. Before the FIB was available, the method for implementing the fix essentially involved running clear back through *the design cycle. The most expensive part of this activity are the generation of new masks, and the fabrication of new wafers. Furthermore, the fabrication of new wafers can take upwards of two months. If an FIB is available, *one can use the FIB to make the modifications on a few prototypes, and the devices are ready for re-testing. By using the FIB circuit edit process, the costs associated with the mask set changes and the fabrication can be eliminated. More importantly, the turn around time can be reduced from several months to several days or less.

6. Our Mission

Education and Training for the Electronics Industry

Semitracks provides education, training, and certification services and products for the electronics industry. We specialize in serving Semiconductor, Microsystems and Nanotechnology suppliers and users. Semitracks Inc. helps engineers, technicians, scientists, and management understand these dynamic fields. We offer courses in Semiconductor Reliability, Test, Packaging, Process Integration, Failure and Yield Analysis, and Focused Ion Beam technology. Learn from the Experts.