2006 September/October Newsletter
Volume 2, Issue 9
Introducing Semitracks Discussion Forums!
The main goal of Semitracks is to provide education and training for the semiconductor industry. There are many ways to learn (colleges/universities, short courses, books, videos, online training), discussion forums can be one of the best methods for gaining knowledge on a specific item. I'm sure many of you participate in other discussion forums.
We are providing these forums as a service to the semiconductor industry. Although there are other discussion forums that touch on semiconductor technology, there is not a good place for scientists, engineers, and technicians to discuss everyday problems and challenges they encounter.
So please participate. Ask questions, and if you have experience or knowledge pertaining to someone else's post, please respond.
2. Upcoming Conferences
International Symposium for Testing and Failure Analysis
November 12-16, 2006 Renaissance Austin Hotel in Austin, TX
For more information, click here.
3. Course Schedule
Invest in yourself and your staff. Time is running short to enroll in our Summer courses on Packing Technology, Packaging Design, Process Integration, Reliability, and Failure and Yield Analysis. Come and learn from the experts!
Semiconductor Process Integration
Semitracks, along with Semiconductor International, have put together a two-day course on Semiconductor Process Integration for CMOS and BiCMOS Technologies. Dr. Badih El-Kareh of Texas Instruments will give an overview of the process integration challenges associated with today's advanced semiconductor devices. Dr. El-Kareh will cover passive and active components, contact and interconnect issues, isolation technologies such as STI and SOI, transistor integration issues, as well as full CMOS, BiCMOS and high speed bipolar process integration techniques. To learn more, click on the link below to visit the course page.
- (January 29-31, 2007) - Tempe, Arizona
This intensive 4-day course offers a comprehensive examination of the wafer fab processes used to manufacture state-of-the-art microchips. Topics include semiconductor devices and ICs, silicon crystal growth and crystal defects, ion implantation, thermal processing, contamination control, wafer cleaning, LPCVD, PECVD, PVD, CMP, microlithography, etch, multilevel interconnect technology, and manufacturing technology. Process integration will be illustrated using a basic CMOS process flow.
The course is designed primarily for process engineers and process technicians. The emphasis is on understanding how each individual process step works, and understanding the key process control variables for each step. The functional design of the process tools is also discussed, as are process characterization, monitoring, and control.
Engineers new to semiconductor manufacturing will gain a solid, broad understanding of the entire wafer fab process. Engineers experienced in one or more functional areas of wafer fab will benefit from a thorough understanding of processes in other areas, as well as a better appreciation of process interactions.
- (February 26-March 1, 2007) - Santa Clara, California
Failure and Yield Analysis Course
Failure and Yield Analysis is an increasingly difficult and complex process; engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform failure analysis. This requires knowledge of subjects like: design, testing, technology, processing, materials science, chemistry, and even optics! Failed devices and low yields can lead to customer returns and idle manufacturing lines that can cost a company millions of dollars a day. Your industry needs competent analysts to help solve these problems. This is a multi-day course that offers detailed instruction on a variety of effective tools, as well as the overall process flow for locating and characterizing the defect responsible for the failure.
- (March 12-15, 2007) - Santa Clara, California
Semiconductor reliability is at a crossroads. In the past, reliability meant discovering, characterizing and modeling failure mechanisms and determining their impact on the reliability of the circuit. Today, reliability can involve tradeoffs between performance and reliability, assessing the impact of new materials, dealing with limited margins, etc. Analysis and experimentation is now performed at the wafer level instead of the packaging level. This requires knowledge of subjects like: design of experiments, testing, technology, processing, materials science, chemistry, and customer expectations. While reliability levels are at an all-time high level in the industry, rapid changes may quickly cause reliability to deteriorate. Your industry needs competent engineers and scientists to help solve these problems.
- (March 27-29, 2007) - Santa Clara, California
Packaging Technology and Challenges
Semitracks, Inc. and Semiconductor International have put together a course which will provide an overview of the current business climate, anticipated trends and the associated impact on assembly/packaging roadmaps. There will be an in depth discussion of both high-end CPU roadmaps plus the roadmaps to address the multitude of communications and network devices that are driving the digital revolution.
- (April 9-10, 2007) - Tempe, Arizona
Packaging Design and Modeling
Semitracks, Inc. and Semiconductor International have assembled a course on IC Packaging Design and Modeling. This course provides an overview of the packaging design process. The course covers current packaging technologies, including chip scale packaging, Ball Grid Array technology and other current concepts. This class focuses on techniques and the importance of thermal and mechanical simulations. Discussions and examples will concentrate on thermal performance simulations, assembly & packaging stresses, package reliability (including solder joint fatigue simulation), and interactions between chip and package. In addition, a special section will be examples of successful wafer level simulations.
- (April 11-13, 2007) - Tempe, Arizona
We offer other courses as well as in-house courses. For more information, visit our website at http://www.semitracks.com.
4. Semitracks Segment of the Month
Semitracks’ new and improved online training is convenient, up-to-date, and cost effective. Access the same material presented in our courses whenever you need it, right when you need it without having to worry about the high costs and hassle of traveling. The semiconductor field is an ever-changing one. With access to the most current information, you can stay on top of the new technology. Online training is also very cost effective. For only $500 per year, you gain access to thousands of dollars worth of courses and course material.
Give our online training a try – for free. This month’s topic is Transistor Isolation Schemes.
Transistor isolation is key to cramming more transistors on a single chip. The two leading isolation schemes are LOCOS (LOCal Oxidation of Silicon) and STI (Shallow Trench Isolation). For an overview of this important topic, click here.
Sign up to access all of Semitracks online training at http://www.semitracks.com/default.htm and “Learn from the Experts” when it’s convenient for you.
5. Technical Tidbit
Oxide Reliability Projection
Reliability projections for oxides requires more than just experimentation. After the experimentation is complete, the engineer must make a calculation as to the lifetime of the oxides on the component. Here is how the reliability engineer makes a projection. You need to know voltage, temperature, area scaling, and the distribution very accurately. In the graph shown here, the measured data is on the right. The measurement time might be in hours or tens of hours. The engineer will use a high voltage or electric field, possibly a high temperature and collect data. Hopefully, one can draw a straight line through the data, to define the voltage acceleration. This becomes the model. Then one must correct for area because the test structures have a much different area than the actual transistor gate dielectrics. This reduces the lifetime of the oxide substantially. Next, we need to account for the statistics of breakdown. The time-to-failure of the individual gate dielectrics is dispersed. In a 10 million transistor IC, some dielectrics will fail before others. We need to account for the ones that might fail early. Also, we need to account for the fact that some ICs might fail before others do. Let’s say we need to achieve a failure rate of less than 100 parts per million. This reduces the lifetime further. We also need to account for different operating temperatures. While the engineer might have tested at 25°C, the product may actually operate at 50 or 75°C. This reduces the lifetime even further. We then arrive at the correct extrapolation. Therefore, the area, distribution, temperature, and voltage acceleration must be accurate. These must be known quite accurately in order to give the customer a reasonable reliability projection number. Even so, the reliability projection number is inaccurate. Most IC manufacturers can provide about one significant digit accuracy.
6. Our Mission
Education and Training for the Electronics Industry
Semitracks provides education, training, and certification services and products for the electronics industry. We specialize in serving Semiconductor, Microsystems and Nanotechnology suppliers and users. Semitracks Inc. helps engineers, technicians, scientists, and management understand these dynamic fields. We offer courses in Semiconductor Reliability, Test, Packaging, Process Integration, Failure and Yield Analysis, and Focused Ion Beam technology. Learn from the Experts, Semitracks.