2007 June Newsletter

Volume 3, Issue 6

June 2007

Welcome to the Semitracks Online Monthly Newsletter! It is our goal that you find this newsletter interesting, informative and useful. Please email any comments or feedback to This email address is being protected from spambots. You need JavaScript enabled to view it. .

1. News

Upcoming Courses at Semicon West

Semitracks is offering two must-attend courses discussing two critical topics facing the semiconductor industry:

Reliability Challenges for Advanced ICs

Advanced Thermal Management and Packaging Materials

Reliability Challenges for Advanced ICs

The continued scaling of gate dielectric thickness has resulted in increased leakage current and shrinking reliability margins. Designers must balance circuit performance with device reliability. The introduction of high-k dielectric materials to reduce gate leakage current presents significant challenges for electrical and reliability characterization. Bulk trapping complicates electrical measurements and wear-out mechanisms are not yet understood. An overview of thin gate oxide reliability will be presented and issues relating to high-k gate oxide reliability will be discussed.

The scaling of transistors exacerbates hot carrier effects. One particularly difficult challenge is overcoming the effects of Negative Bias Temperature Instability (NBTI), and more recently, Positive Bias Temperature Instability (PBTI). Both NBTI and PBTI can degrade the performance of the p-channel transistor. Boron penetration from the polysilicon gate strongly affects NBTI. Both are also difficult to combat through standard processing techniques.

To improve IC performance, copper metallization and Low-K dielectrics are routinely used in advanced processes. Copper metallization exhibits different electromigration, stress voiding and corrosion behavior than traditional aluminum-based interconnect systems. The mechanical, thermal, and electrical issues due to copper and its integration with Low-K dielectrics will be discussed. Low-K dielectrics exhibit inferior thermal, mechanical, and dielectric breakdown characteristics compared to traditional silicon dioxide and silicon nitride-based materials.

Dr. John Suehle of the National Institute of Standards and Technology and Dr. Jeffrey Gambino of IBM, two leading researchers and lecturers in field of Semiconductor Reliability, will give an overview of the problems and reliability challenges associated with today's advanced semiconductor devices. Dr. Suehle will cover front-end reliability issues including: Hi-K dielectrics, Negative Bias Temperature Instability, and Positive Bias Temperature Instability. Dr. Gambino will cover back-end reliability issues including: copper metallization, electromigration, stress induced voiding, and Lo-K dielectric breakdown.

Reliability and Characterization Challenges for Advanced ICs

  • (July 17, 2007) - San Francisco, California (in Moscone Center at Semicon West)

Advanced Thermal Management and Packaging Materials

Advanced materials are becoming critical for today's microelectronic systems. As new, more powerful chip designs are introduced, they consume more power. This has made thermal management an important concern in today's high performance systems. Systems ranging from active electronically scanned radar arrays to web servers require components that can dissipate heat efficiently. This requires materials capable of dissipating heat and maintaining compatibility with the package and die.

In response to critical needs, there have been revolutionary advances in thermal management materials in the last few years. There are now over 15 low-CTE, low-density materials with thermal conductivities ranging between 400 and 1700 W/m-K, and many others with somewhat lower conductivities. Some are low cost. Others have the potential to be low cost in high-volume. Production applications include servers, laptops, PCBs, PCB cold plates/heat spreaders, cellular telephone base stations, hybrid electric vehicles, power modules, phased array antennas, thermal interface materials (TIMs), optoelectronic telecommunication packages, laser diode and LED packages, and plasma displays.

This course covers the large and increasing number of advanced thermal management materials, providing an in-depth discussion of properties, manufacturing processes, applications, cost, lessons learned, typical development programs, and future directions. Traditional materials are discussed for reference. Participants are invited to bring their thermal management problems for discussion.

Advanced Thermal Management and Packaging Materials

  • (July 18, 2007) - San Francisco, California (in Moscone Center at Semicon West)

2. Course Schedule

Invest in yourself and your staff. Our Summer and Fall 2007 schedule is now available, come and learn from the experts!

CMOS and BiCMOS Process Integration

Semitracks has put together a three-day course on Semiconductor Process Integration for CMOS and BiCMOS Technologies. Dr. Badih El-Kareh, an independent consultant and the architect of numerous CMOS and BiCMOS processes, will give an overview of the process integration challenges associated with today's advanced semiconductor devices. Dr. El-Kareh will cover passive and active components, contact and interconnect issues, isolation technologies such as STI and SOI, transistor integration issues, as well as full CMOS, BiCMOS and high speed bipolar process integration techniques. Learn from one of the industry leaders on this topic. To learn more, click on the link below to visit the course page.

Process Integration

  • (September 24-26, 2007) - Dresden, Germany
  • (October 22-24, 2007) - Austin, Texas

Wafer Fab Processing

This new intensive 4-day course offers a comprehensive examination of the wafer fab processes used to manufacture state-of-the-art microchips. Topics include semiconductor devices and ICs, silicon crystal growth and crystal defects, ion implantation, thermal processing, contamination control, wafer cleaning, LPCVD, PECVD, PVD, CMP, microlithography, etch, multilevel interconnect technology, and manufacturing technology. Process integration will be illustrated using a basic CMOS process flow.

The course is designed primarily for process engineers and process technicians. The emphasis is on understanding how each individual process step works, and understanding the key process control variables for each step. The functional design of the process tools is also discussed, as are process characterization, monitoring, and control.

Engineers new to semiconductor manufacturing will gain a solid, broad understanding of the entire wafer fab process. Engineers experienced in one or more functional areas of wafer fab will benefit from a thorough understanding of processes in other areas, as well as a better appreciation of process interactions.

Each student will also receive a copy of Microchip Manufacturing by Stan Wolf. This unique, full color book is a "must have" reference text for anyone working in the semiconductor industry.

Semiconductor Processing

  • (September 17-20, 2007) - Dresden, Germany
  • (October 15-18, 2007) - Austin, Texas

Failure and Yield Analysis

Semitracks, along with Test and Measurement World, have put together a four-day course on Failure and Yield Analysis. Failure and Yield Analysis is an increasingly difficult and complex process; engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform failure analysis. This requires knowledge of subjects like: design, testing, technology, processing, materials science, chemistry, and even optics! Failed devices and low yields can lead to customer returns and idle manufacturing lines that can cost a company millions of dollars a day. Your industry needs competent analysts to help solve these problems. This is a multi-day course that offers detailed instruction on a variety of effective tools, as well as the overall process flow for locating and characterizing the defect responsible for the failure.

Failure and Yield Analysis

  • (June 18-22, 2007) - Penang, Malaysia
  • (July 2-6, 2007) - Shanghai, China
  • (July 9-13) - Bangkok, Thailand

To register for our courses, register online or download the registration form. You can fax the completed form to Semitracks at (505) 858-9813, or call (505) 858-0454 to register by phone.

We offer other courses as well as in-house courses. For more information, visit our website at http://www.semitracks.com.

3. Semitracks Segment of the Month

Semitracks’ new and improved online training is convenient, up-to-date, and cost effective. Access the same material presented in our courses whenever you need it, right when you need it without having to worry about the high costs and hassle of traveling. The semiconductor field is an ever-changing one. With access to the most current information, you can stay on top of the new technology. Online training is also very cost effective. For only $500 per year, you gain access to thousands of dollars worth of courses and course material.

Give our online training a try – for free. This month’s topic is Transistor Isolation Schemes.

Transistor isolation is key to cramming more transistors on a single chip. The two leading isolation schemes are LOCOS (LOCal Oxidation of Silicon) and STI (Shallow Trench Isolation). For an overview of this important topic, click here.

Sign up to access all of Semitracks online training at http://www.semitracks.com/default.htm and “Learn from the Experts” when it’s convenient for you.

4. Technical Tidbit


In order to design an effective circuit for ESD protection, one must understand the behavior of the MOSFET under the extreme conditions of an ESD event. This picture shows a typical IV characteristic during an ESD pulse. As the voltage increases across a MOSFET, the device reaches a point where it enters snapback, a negative resistance regime where the current increases sharply and the voltage comes down. If the current is allowed to increase, the device will reach a point where second breakdown and permanent damage occurs. The goal is to prevent the internal transistors from reaching this condition. Therefore we design circuits that can trigger at lower voltages and provide a bypass for the current. We can also design transistors susceptible to ESD with higher breakdown voltages and the ability to withstand higher current levels.

5. Our Mission

Education and Training for the Electronics Industry

Semitracks provides education, training, and certification services and products for the electronics industry. We specialize in serving Semiconductor, Microsystems and Nanotechnology suppliers and users. Semitracks Inc. helps engineers, technicians, scientists, and management understand these dynamic fields. We offer courses in Semiconductor Reliability, Test, Packaging, Process Integration, Failure and Yield Analysis, and Focused Ion Beam technology. Learn from the Experts, Semitracks.