IC Packaging Technology and Challenges Notes

Semitracks, Inc. has put together a course which will provide an overview of the current business climate, anticipated trends, and the associated impact on assembly/packaging roadmaps. There will be an in-depth discussion of both high-end CPU roadmaps plus the roadmaps to address the multitude of communications and network devices that are driving the digital revolution. The course will generically address typical assembly flows and cost implications for both wafer fabrication and assembly, with special focus on what the low-cost alternatives will be in both camps.

Based on the technical reliability issues that the packaging roadmaps drive, such as thin film delamination/cracking, bump cracks, via delamination/cracking, thermal interface degradation, heat sink retention, and socketing issues, there will be a review of commonly used failure analysis tools and techniques appropriate to each failure mechanism. Thus, state-of-the-art, non-destructive imaging tools of acoustics, x-ray, scanning SQUID microscopy, and terahertz imaging will be reviewed with respect to advantages, limitations, and likely evolution to next generation. Other techniques that will be discussed are time domain reflectometry (TDR), adhesion testing, thin film materials characterization, and disassembly techniques to allow fault isolation and failure analysis. The course will cover the impact of next-generation technologies such as Cu, ultra low-k dielectrics, 300mm wafer fabrication, wafer scale packaging, embedded passives, chip on board, and modular integration. Finally, the course will hint at the future, with a focus on Nanotechnology, Connectintelligence, and the currently ill thought-out arena of what packaging/assembly means for this era of molecular devices.

This course is recommended for engineers and scientists involved in setting the direction for adapting to the rapidly exploding arena of assembly/packaging in the digital revolution. This course will also be especially useful to engineers and scientists actively engaged in performing risk assessments on packaging technologies, performing fault isolation and failure analysis, and performing stressing to achieve reliability certification of such technologies.

Pricing

Description Price
IC Packaging Technology and Challenges Course Notes $100

Order Form for Manuals (Printable Version)

Please note that shipping fees do not necessarily represent UPS published rates and may include handling charges levied by this store.

Home Products Notes IC Packaging Technology and Challenges Notes