Reliability and Characterization Challenges Notes
The continued scaling of gate dielectric thickness has resulted in increased leakage current and shrinking reliability margins. Designers must balance circuit performance with device reliability. The introduction of high-k dielectric materials to reduce gate leakage current presents significant challenges for electrical and reliability characterization. Bulk trapping complicates electrical measurements and wear-out mechanisms are not yet understood. An overview of thin gate oxide reliability will be presented and issues relating to high-k gate oxide reliability will be discussed.
The scaling of transistors exacerbates hot carrier effects. One particularly difficult challenge is overcoming the effects of Negative Bias Temperature Instability (NBTI) and, more recently, Positive Bias Temperature Instability (PBTI). Both NBTI and PBTI can degrade the performance of the p-channel transistor. Boron penetration from the polysilicon gate strongly affects NBTI. Both are also difficult to combat through standard processing techniques.
To improve IC performance, copper metallization and Low-K dielectrics are routinely used in advanced processes. Copper metallization exhibits different electromigration, stress voiding, and corrosion behavior than traditional aluminum-based interconnect systems. The mechanical, thermal, and electrical issues due to copper and its integration with Low-K dielectrics will be discussed. Low-K dielectrics exhibit inferior thermal, mechanical, and dielectric breakdown characteristics compared to traditional silicon dioxide and silicon nitride-based materials.
|Reliability and Characterization Challenges Course Notes (2007)||$100|
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