Terms A-C

A

acceptor n - in a semiconductor, an impurity in a semiconductor that accepts electrons excited from the valence band, leading to hole conduction. [SEMI M1-94 and ASTM F1241] Also see hole.

access time n - a time interval that is characteristic of a storage device and is essentially a measure of the time required to communicate with that device. [IEEE]

accumulation condition n - the region of the capacitance-voltage (C-V) curve for which a 5-V increment toward a more negative voltage for p-type material, or toward a more positive voltage for n-type material, results in a change of less than 1% in the maxi­mum capacitance, Cmax . [ASTM F1241]

active area n - the region of thin oxide on a die or wafer in which transistors and other circuits reside. [SEMATECH]

active devices n - semiconductor devices that have active function, such as integrated circuits and transistors. [SEMI G35-87] Con­trast passive devices.

adhesion, resist edge n - the ability of the edge of an image in a developed resist coating to adhere to its substrate under applied physical or chemical stress. [ASTM F127-84]

adhesive stringer n - on a photolithographic pellicle, any detectable protrusion from the edge of the adhesive. [SEMI P5-94]

aeolotropic - see anisotropic.

AES (Auger-electron spectrometry)/AES (Atomic-emission spectroscopy)/SAM (Scanning Auger microprobe) - see Auger electron spectroscopy.

AFM - see atomic force microscopy.

alignment n 1 - the accuracy of the relative position of an image on a reticle with reference to an existing image on a substrate. [SEMATECH] 2 - a procedure in which a wafer is correctly posi­tioned relative to a reticle. [SEMATECH] 3 - the mechanical positioning of reference points on a wafer or flat panel display substrate (also called alignment marks or alignment targets) to the corresponding points on the reticle or reticles. The measure of alignment is the overlay at the positions on the wafer or sub­strate where the alignment marks are placed. [Adapted from SEMI P18-92 and D8-94] Also see direct alignment and indirect alignment.

alloy n 1 - a composite of two or more elements, of which at least one is metal. [SEMATECH] 2 - a thermal cycle in which two or more discrete layers (of which at least one is metal) react to allow good electrical contacts. [SEMATECH]

aluminized area n - in a cerdip or cerpack semiconductor package, the leadframe area coated with aluminum to provide a surface suitable for wire bonding. The maximum area is defined by the inside dimension of the cap or ceramic ring. In some cases, the die attach area is also coated if a full leadframe is used. The coat­ing may be vacuum deposited or bonded. [SEMATECH]

aluminized width n - in a semiconductor package, the width of the area coated with a protective layer of aluminum. This area cov­ers most of the top formed width. [SEMATECH] Also see pack­age, bond finger, top formed width, and aluminized area.

ambient temperature (TA) 1 - the temperature of the surrounding medium, such as air or liquid, that comes into contact with the device or apparatus. [SEMATECH] 2 - the temperature of the specified, surrounding medium (such as air, nitrogen, or a liquid) that comes into contact with a semiconductor device being tested for thermal resistance. [SEMI G38-87]

ammonium fluoride (NH4 F) - a white crystalline salt used to buffer hydrofluoric acid etches that dissolve silicon dioxide but not silicon. An example of such an etch is the buffered oxide etch. [SEMATECH] Also see pinhole.

ammonium hydroxide (NH4 OH) - a weak base formed when ammonia is dissolved in water. [SEMATECH]

amorphous silicon - silicon with no discernible crystalline structure. [SEMATECH] Contrast polycrystalline silicon.

analog adj - A signal in an electronic circuit that takes on a continu­ous range of values rather than only a few discrete values; a cir­cuit or system that processes analog signals. [1994 National Technology Roadmap for Semiconductors] Contrast discrete.

angle-resolved scattering (ARS) n - technique that measures light scattered from particles as a function of angle; used to character­ize particles. [SEMATECH]

angstrom (Å) n - unit of linear measure equal to one ten billionths of a meter (10 -10 m). (The diameter of a human hair is approxi­mately 750,000 Å.) The preferred SI unit is nanometers. 10 Å = 1 nm. [SEMATECH]

anion n - an ion that is negatively charged. [SEMATECH]

anisotropic adj - exhibiting different physical properties in different directions. NOTE: In semiconductor technology, the different directions are defined by the crystallographic planes. [SEMI M1: 94 and ASTM F1241] Also called nonisotropic and aeolotropic. Also see anisotropic etch.

anisotropic etch n - a selective etch that exhibits an accelerated etch rate along specific crystallographic planes. NOTE—Anisotropic etches are used to determine crystal orientation, to expose crystal defects, and to facilitate dielectric component isolation. [SEMI M1-94 and ASTM F1241] Also called preferential etch. Also see anisotropic.

anneal n - a high-temperature operation that relieves stress in silicon, activates ion-implanted dopants, reduces structural defects and stress, and reduces interface charge at the silicon-silicon dioxide interface. [SEMATECH]

anomaly - see defect.

antireflective coating (ARC) n - a layer of dielectric material depos­ited on a wafer before resist to minimize reflections during resist exposure. [SEMATECH]

ARC - see antireflective coating.

architecture n - of a computer system, a defined structure based on a set of design principles. The definition of the structure includes its components, their functions, and their relationships and inter­actions. [SEMATECH]

area contamination n - foreign matter on localized portions of a wafer or substrate surface. [SEMI M3-88]

artifact n 1 - a physical standard against which a parameter is mea­sured; for example, a test wafer used for testing parametric drift in a machine. [SEMATECH] Also called standard reference material. 2 - a superficial or unessential attribute of a process or characteristic under examination; for example, a piece of lint on a lens that appears through a microscope to be a defect on a die. [SEMATECH] 3 - in surface characterization, any contribution to an image from other than true surface morphology. Examples include contamination, vibration, electronic noise, and instru­ment imperfections. [SEMATECH]

ash v - to apply heat to a material until the material has been reduced to a mineral residue. [SEMATECH]

asher n - a machine used to remove resist from substrates. [SEMAT­ECH]

ashing n - the operation of removing resist from a substrate by oxida­tion; a reaction of resist with oxygen to remove the resist from the substrate. [SEMATECH]

aspect ratio n 1 - in etch, the depth-to-width ratio of an opening on a wafer. [SEMATECH] 2 - in feature profile, the height-to-width ratio of a feature. [SEMATECH]

atomic force microscopy (AFM) n - a microscopy technique based on profilometry using an atomically sharp probe that provides three-dimensional highly magnified images. During AFM, the probe scans across a sample surface. The changes in force between the sample and the probe tip cause a deflection of the probe tip that is monitored and used to form the magnified image. [SEMATECH]

atomic percent n - in electron spectroscopy for chemical analysis (ESCA) of plastic surface composition, the number of atoms of a particular element present in every hundred atoms within the ESCA detection volume. [SEMATECH]

ATPG - see automatic test pattern generation.

at-speed test n - any test performed on an integrated circuit that tests the device at its normal operating clock frequency. [1994 National Technology Roadmap for Semiconductors]

Auger electron spectroscopy (AES) n - the energy analysis of Auger electrons produced when an excited atom relaxes by a radiationless process after ionization by a high-energy electron, ion, or X-ray beam. [SEMATECH]

Auger process n - the radiationless relaxation of an atom involving a vacancy in an inner electron shell. An electron is emitted, which is referred to as an Auger electron. [ASTM E673-90]

autodoping n - in the manufacture of silicon epitaxial wafers, the incorporation of dopant originating from the substrate into the epitaxial layer. [SEMI M1-94 and ASTM F1241] Also called self-doping. Also see doping and substrate.

automatic test pattern generation (ATPG) n - the automatic development of vectors that, when applied to an integrated circuit, permit faults to be detected in the performance of the integrated circuit. [1994 National Technology Roadmap for Semiconductors]

B

back-end of line (BEOL) n - process steps from contact through completion of the wafer prior to electrical test. Also called back end. [SEMATECH]

backgrind n - an operation using an abrasive on the back side of a substrate to achieve the necessary thinness for scribing, cutting, and packaging of die. [SEMATECH]

back oxide n - a layer of silicon dioxide formed on the back of a wafer during oxidation. [SEMATECH]

backside - see back surface.

back surface n - of a semiconductor wafer, the exposed surface opposite to that on which active semiconductor devices have been or will be fabricated. [ASTM F1241] Also called backside.

bake n - in wafer manufacturing, a process step in which a wafer is heated in order to harden resist, remove moisture, or cure a film deposited on the wafer. [SEMATECH]

ball-grid array (BGA) n - an integrated circuit surface mount package with an area array of solder balls that are attached to the bottom side of a substrate with routing layers. The die is attached to the substrate using die and wire bonding or flip-chip interconnection. [SEMATECH] Also called land-grid array, pad-grid array, or pad-array carrier.

bar - see die, crossbar, and bar end.

bare die n - individual, unpackaged silicon integrated circuit. [1994 National Technology Roadmap for Semiconductors]

barrier n - a physical layer designed to prevent intermixing of the layers above and below the barrier layer; for example, titanium - tungsten and titanium-nitride layers. [SEMATECH]

barrier layer - see depletion layer.

base n 1 - in semiconductor manufacturing chemicals, a substance that dissociates in water to liberate hydroxyl ions, accepts a pro­ton, has an unshared pair of electrons, or reacts with acid to form a salt. A base has a pH greater than seven and turns litmus paper blue. [SEMATECH] 2 - in facilities and safety, a corrosive material with the chemical reaction characteristic of an electron donor. [SEMI S4-92] 3 - in quartz and high temperature carriers, the material at the bottom of a wafer carrier on which the wafer carrier rests when placed on a flat surface. [SEMI E2-93] 4 - of a cerdip or cerpack package, the bottom ceramic portion. A leadframe, a window frame, and the cap are attached to the base— generally with devitrifying solder glass—during package/device manufacture. [SEMI G1-85] Also see cap and window frame.

behavioral n - a level of logic design that involves describing a system at a level of abstraction that does not involve detailed circuit elements, but instead expresses the circuit functionality linguistically or as equations. [1994 National Technology Roadmap for Semiconductors]

BEOL - see back-end of line.

BGA - see ball grid array.

biCMOS design n - the combination of bipolar and complementary metal oxide semiconductor design and processing principles on a single wafer or substrate. [SEMATECH]

bimetal mask - see mask, bimetal.

binding energy n - the value obtained by subtracting the instrumentally measured kinetic energy of an electron from the energy of the incident photon, corrected for an instrument work function. [SEMATECH]

bipolar technology n - a semiconductor device fabrication technology that produces transistors which use both holes and electrons as charge carriers. [SEMI M1-94 and ASTM F1241]

bird’s beak n - a structural feature produced as a result of the lifting of the edges of the nitride layer during subsequent oxidation. [SEMATECH]

BIST - see built-in self test.

blister ceramic n - an enclosed, localized separation within or between the layers of a ceramic package that does not expose an underlying layer of ceramic or metallization. [SEMI G61-94] Also called bubble ceramic.

blister metal n - in packaging, an enclosed, localized separation of a metallization layer from its base material (such as ceramic or another metal layer) that does not expose the underlying layer. [SEMI G8-94] Also called bubble metal, blister metallization, and bubble metallization. Also see package.

bonding pad n - relatively large metal areas on a die used for electrical contact with a package or probe pins. [SEMATECH]

boundary scan n - a scan path that allows the input/output pads of an integrated circuit to be both controlled and observed. [1994 National Technology Roadmap for Semiconductors]

bridge n 1 - a defect in which two adjacent areas connect because of misprocessing such as poor lithography, particle contamination, underdevelopment, or etch problems. [SEMATECH] Also called short. 2 - software that allows access to, and combination of, data from incompatible databases. [SEMATECH]

bridging fault n - a fault modeled as a short-circuit between two nets on a die. [1994 National Technology Roadmap for Semiconductors]

brightfield illumination n (transmission electron microscopy) - the illumination of an object so that it appears on a bright background. [ASTM E7-93]

buffered hydrofluoric acid n - an extremely hazardous corrosive used to etch silicon dioxide from a wafer. This acid has a 20 to 30-minute reaction delay after contact with skin or eyes. [SEMATECH]

built-in self test (BIST) - any of the methods of testing an integrated circuit (IC) that use special circuits designed into the IC. This circuitry then performs test functions on the IC and signals whether the parts of the IC covered by the BIST circuits are working properly. [1994 National Technology Roadmap for Semiconductors]

buried contact n - a conductive region between two less conductive regions. [SEMATECH]

buried layer n 1 - a conductive layer between two less conductive films; for example, a localized n+ region in a p-type wafer that reduces the npn collector series resistance for integrated circuit transistors fabricated in an n-type epitaxial layer deposited on the p-type wafer. [SEMATECH] 2 - in epitaxial silicon wafers, a dif­fused region in a substrate that is, or is intended to be, covered with an epitaxial layer. [SEMI M18-94 and ASTM F1241] Also called subdiffused layer and diffusion under film.

burn-in n - the process of exercising an integrated circuit at elevated voltage and temperature. This process accelerates failure normally seen as “infant mortality” in a chip. [1994 National Technology Roadmap for Semiconductors] Also see infant mortality.

C

C4 (controlled collapse chip connect) - see flip chip.

cap deposition - see passivation.

carrier n 1 - an entity capable of carrying electric charge through a solid; for example, mobile holes and condition electrons in semi­conductors. [SEMI M1-94 and ASTM F1241] Also called charge carrier. Also see majority carrier and minority carrier. 2 - slang for wafer carrier. [SEMATECH]

cavity-down packages n - in cofired ceramic packages, packages on which the die surface faces the mounting board. [SEMI G61-94]

cavity-up packages n - in cofired ceramic packages, packages on which the die surface faces away from the mounting board. [SEMI G61-94]

cerdip - abbreviation for ceramic dual-in-line package. See dual-in-line package.

cerpack - abbreviation for ceramic package.

channel n.- a control region through which the principal current charge pass and whose cross-section is determined by the voltage applied to a gate, the principal current being the result of an applied field [JESD77].

chemical-mechanical polish (CMP) n - a process for the removal of surface material from a wafer. The process uses chemical and mechanical actions to achieve a mirror-like surface for subse­quent processing. [SEMI M1-94 and ASTM F1241] Also called chem-mech polish.

chemical vapor deposition (CVD) n - in semiconductor technology, a process in which a controlled chemical reaction produces a thin surface film. [SEMI M1-94 and ASTM F1241] Contrast physical vapor deposition.

chem-mech polish - See chemical-mechanical polish.

chip n 1 - in semiconductor wafers, a region where material has been unintentionally removed from the surface or edge of the wafer. [ASTM F1241] Contrast indent. 2 - see die. 3 - in packaging, a region of material missing from a component; for example, ceramic from a package or solder from a preform. The region does not progress completely through the component and is formed after the component is manufactured. The chip size is given by its length, width, and depth from a projection of the design plan-form. [SEMI G61-94] Also called chip-out. Contrast pit. 4 - in flat panel display substrates, a region of material miss­ing from the edge of the glass substrate, which is sometimes caused by breakage or handling. [SEMI D9-94]

chip carrier (CC) 1 n - a small footprint semiconductor package gen­erally with terminals on all four sides. The package may be man­ufactured by cofired ceramic or multilayer printed circuit board technologies. [SEMATECH] 2 n - a low profile package whose chip cavity or mounting area occupies a major fraction of the package area and whose terminals consist of metal pad surfaces (on the leadless versions) or leads formed around the sides and under the package or out from the package (on leaded versions) [JESD99, JESD30]. Also see castellation and ceramic chip carrier.

chip-out - synonym for chip (see definition 1).

circuit n - the combination of a number of connected electrical ele­ments or parts to accomplish a desired function. [SEMATECH]

circuit design n - techniques used to connect active (transistors) and passive (resistors, capacitors, and inductors) elements in a man­ner to perform a function (that is, logic, analog). [1994 National Technology Roadmap for Semiconductors]

circuit geometries n - the relative shapes and sizes of features on a die. [SEMATECH]

CMOS - see complementary metal oxide semiconductor.

CMP - see chemical-mechanical polish.

comet n - on a substrate, a buildup of resist shaped like a comet and generated by a defect. [SEMI P3-90] Also called motorboat.

complementary metal oxide semiconductor (CMOS) technology 1 n - a fabrica­tion process that incorporates p-channel and n-channel MOS transistors within the same silicon substrate. [SEMATECH] 2 n - a technology for combining p-channel and n-channel transistors in a single chip integrated circuit [JESD99].

component n 1 - an individual electronic part, such as a device, diode, or capacitor that is fabricated in a metal oxide semicon­ductor or bipolar process. [SEMATECH] 2 - an individual piece or a complete assembly of individual pieces, including industrial products that are manufactured as independent units, capable of being joined with other pieces or components. The typical com­ponents referred to by the specification are valves, fittings, regu­lators, gauges, instrument sensors, a single length of tubing, everal pieces of tubing welded together, tubing welded to fit­tings, and the like. [SEMI F1-90] 3 - the fundamental parts of an object, its entities, or relationships. [SEMATECH] 4 - the hard­ware and software that work in sets (functional entities) to per­form the operation(s). [SEMATECH]

conchoidal fracture n - a fracture having smooth convexities and concavities like a clamshell. [SEMATECH] Also see chip.

conductor n - a substance through which electricity can readily flow. Contrast insulator. [SEMATECH]

contact n - in an oxide layer, an opening that allows electrical con­nection between metal and silicon layers. [SEMATECH] Also see window and via.

contamination n 1 - the presence of particles, chemicals, and other undesirable substances, such as on or in a process tool, in a pro­cess liquid, or in a cleanroom environment. [SEMATECH] Also see area contamination and particulate contamination. 2 - three-dimensional foreign material adhering to a package (plastic or ceramic) or leadframe, or parent material displaced from its nor­mal location and similarly adhered. Adherence means that the particle cannot be removed by an air or nitrogen blast at 20 psi. [SEMATECH] Also see foreign material and stain.

controlled collapse chip connect (C4) - see flip chip

correlation n 1 - a relation existing between phenomena or things or between mathematical or statistical variables which tend to vary, be associated, or occur together in a way not expected on the basis of chance alone. [Webster’s Dictionary]

crack n 1 - on semiconductor wafers, a cleavage or fracture that extends to the surface and may or may not pass through the entire thickness of the wafer. [ASTM F1241] 2 - of a semicon­ductor package or solder preform, a cleavage or fracture that extends to the surface. The crack may or may not pass through the entire thickness of the package or preform. [SEMI G61-94] 3 - in flat panel display substrates, a fissure located at the sheet edge or central area. [SEMI D9-94]

crater n - on the surface of a slice or wafer, an individually distin­guishable bowl-shaped cavity. A crater is visible when viewed under diffused illumination. [SEMATECH]

cratering n - on a slice or wafer, a surface texture of irregular closed ridges with smooth central regions. [ASTM F1241]

crescents n - structures with parallel major axes, attributed to sub­strate defects either above or below the surface plane of silicon substrates after epitaxial deposition. [ASTM F1241] Also see fishtails.

critical area n - the area in which the center of a defect must occur to cause a failure or fault. [SEMATECH] Also see fault and fault probability.

critical dimension (CD) n - the width of a patterned line or the dis­tance between two lines, monitored to maintain device perfor­mance consistency; that dimension of a specified geometry that must be within design tolerances. [ASTM F127-84] Also see lin­ewidth.

crosstalk n - the undesirable addition of one signal to another in a circuit usually caused by coupling through parasitic elements. An example would be inductive or capacitive coupling between adjacent conductors. [1994 National Technology Roadmap for Semiconductors]

crossunder n - on a die, the point at which a conductor crosses under a second conductor without making electrical contact. [SEMAT­ECH]

crow’s foot n - on a semiconductor wafer, intersecting cracks in a pattern resembling a “crow’s foot” Y on {111} surfaces and a cross “+” on {100} surfaces. [ASTM F1241]

crystal n - a solid composed of atoms, ions, or molecules arranged in a pattern that is periodic in three dimensions. [ASTM F1241]

crystal defect n - departure from the regular arrangement of atoms in the ideal crystal lattice. [ASTM F1241] Also see crystal lattice and damage.

crystal indices - see Miller indices. Also see crystallographic nota­tion.

crystal lattice n - in a crystal, the three-dimensional and repeating pattern of atoms. [SEMATECH]

crystallographic notation n - a symbolism based on Miller indices used to label planes and directions in a crystal as follows - (111) plane [111] direction {111} family of planes <111> family of directions [SEMI M1-94 and ASTM F1241]

crystal originated particle (COP) n - a surface depression that is formed during soft alkaline chemical treatment of silicon wafer surfaces that contain crystal defects at or close to the wafer sur­face and that scatters light similarly to a very small particle. [ASTM F1241] Also called surface micro defect.

CTE - see coefficient of thermal expansion.

CVD - see chemical vapor deposition.

cycle time n - (1) the length of time required for a wafer to complete a specified process or set of processes. [SEMATECH] (2) the length of time required to complete a failure analysis job from receipt in the failure analysis lab to the time results (written or verbal) are communicated back to the immediate requestor. [Sandia Labs] Also see equipment cycle, minimum theoretical cycle time, and theoretical cycle time.