Terms G-M


gate n - an electrode that regulates the flow of current in a metal oxide semiconductor transistor. [SEMATECH]

gate electrode n - the electrode of a metal oxide semiconductor field effect transistor (MOSFET); it controls the flow of electrical cur­rent between the source and the drain. [SEMATECH]

gate oxide n - a thin, high-quality silicon dioxide film that separates the gate electrode of a metal oxide semiconductor transistor from the electrically conducting channel in the silicon. [SEMATECH]

glass n - a deposited film of silicon dioxide with additives to adjust coefficient of thermal expansion, color, conductivity, and melt­ing point, generally doped with boron or phosphorus or both. [SEMATECH] Also see silicon dioxide.

groove n - in a semiconductor wafer, a shallow scratch with rounded edges that is usually the remnant of a scratch not completely removed by polishing. [SEMI M1-94 and ASTM F1241]

growth hillock - see pyramid.


hermetic sealn - a coat applied in the final stage of thermal process­ing to seal the ceramic package and to protect the device from the external environment. [SEMATECH]

hillock n - a defect caused by stress that raises portions of a metal (such as aluminum) film above the surface of the film. Localized stress within the metal film may elevate portions of the film through the adjacent dielectric layer, resulting in a metal extru­sion and a short to the next metal layer. [SEMATECH] Also see pyramid.

hole n 1 - of a semiconductor, a mobile vacancy in the electronic valence structure that acts like a positive electron charge with positive mass; the majority carrier in p-type material.[SEMI M1-94 and ASTM F1241] 2 - in plastic and metal wafer carriers, the area through which a pin from another wafer carrier can enter for the transfer of wafers. [SEMI E1-86] Also see wafer carrier.

hot carriers n - those carriers, which may be either electrons or holes, that have been accelerated by the large traverse electric field between the source and the drain regions of a metal oxide semiconductor field-effect transistor (MOSFET). They can jeop­ardize the reliability of a semiconductor device when these carri­ers are scattered (that is, deflected) by phonons, ionized donors or acceptors, or other carriers. The scattering phenomenon can manifest itself as substrate current, gate current, or trapped charges. [SEMATECH] Also see trapped charges.


IC - see integrated circuit.

IDDQ - abbreviation for direct drain quiescent current. An electrical parameter associated with the current of a CMOS integrated circuit when in a static (quiescent) condition, that is, no changing signals applied to the IC.

impact test n - in component testing, a test performed to determine particle contribution as a result of mechanical shock to the com­ponent. [SEMATECH] Also called particle impact noise detec­tion or PIND

implant - see ion implantation.

impurity n - a chemical or element added to silicon to change the electrical properties of the material. [SEMATECH] Also see dopant, ion implantation.

inclusion n - discrete second phases (oxides, sulfides, carbides, inter­metallic compounds) that are distributed in a metal matrix. [SEMATECH]

indent n - on a semiconductor wafer, an edge defect that extends from the front surface to the back surface. [ASTM F1241] Con­trast chip.

insulator n - a substance that will not conduct electricity; for exam­ple, silicon dioxide and silicon nitride. [SEMATECH] Contrast conductor.

integrated circuit (IC) n 1 - two or more interconnected circuit ele­ments on a single die. [SEMATECH] 2 - a fabrication technol­ogy that combines most of the components of a circuit on a single-crystal silicon wafer. [SEMI Materials, Vol. 3, Definitions for Semiconductor Materials]

interference contrast microscope n - a microscope that reveals sur­face details of an object in which there is no appreciable absorp­tion by using the interference between two beams of light. [Adapted from ASTM F1241] Also called Nomarski Interfer­ence Contrast

interlevel dielectrics n - an insulating film between two conductive film layers, as between poly and aluminum or between layers of aluminum. [SEMATECH]

interstitial n - in a crystalline solid, an atom that is not located on a lattice site. [SEMATECH]

intrinsic semiconductor n - a semiconductor in which the density of electrons and holes is approximately equal. [SEMATECH] Con­trast extrinsic semiconductor.

ion implantation (I 2 , II) n - a high-energy process that injects an ionized species such as boron, phosphorus, arsenic, or other ions into a semiconductor substrate. [SEMATECH]

I/O pins n - connections to an integrated circuit through which input and/or output (I/O) signals pass. [1994 National Technology Roadmap for Semiconductors]

isolation n - an electrical separation of regions of silicon on a wafer; for example, boron diffusion to isolate a transistor. [SEMAT­ECH] Also see dielectric isolation.


junction spiking n - the penetration of a junction by aluminum, which occurs when silicon near the junction dissolves in alumi­num and migrates along the interconnect lines. Aluminum then replaces silicon at the junction. [SEMATECH]


Kirkendall void n - voids induced in a diffusion couple between two metals that have different interdiffusion coefficients. [SEMAT­ECH]


large scale integration (LSI) n - the placement of at least 100 active devices on a single die. [JESD99]

laser-scattering light event n - a signal pulse that exceeds a preset threshold, generated by the interaction of a laser beam with a localized light scatterer (LLS) at a wafer surface as sensed by a detector. [ASTM F1241] Also see haze.

layout n 1 - the physical geometry of a circuit or die. [1994 National Technology Roadmap for Semiconductors] 2 - the process of creating the physical geometry of a circuit or die. [1994 National Technology Roadmap for Semiconductors] 3 - see composite drawing.

LDD - see lightly doped drain.

life test n - in semiconductor reliability, a test designed to operate the semiconductor until it fails by elevating both temperature and voltage to accelerate the aging process. [Sandia Labs]

lightly doped drain (LDD) n - a metal-oxide semiconductor (MOS) device design in which the drain doping is reduced to improve breakdown voltage. [SEMATECH]

line defect - see dislocation.

LSI - see large scale integration.


Medium Scale Integration (MSI) n - the placement of at between 12 and 100 active devices on a single die. [JESD99]

metallization void n - the absence of a clad, evaporated, plated, or screen printed metal layer or braze from a designated area. [SEMI G58-94] Also called metal void.

metal void - see metallization void.

MFM-CCI - see magnetic current imaging.

microchip - see die.

moon crater n - on a semiconductor wafer, surface texture that results when a wafer floats during the initial stages of chemical polishing in a rotating cup etcher. [ASTM F1241]

motorboat - see comet.

mottled adj - pertaining to the existence on a wafer of material in a window that prevents the window from being properly opened. [SEMATECH]

mound n - on a semiconductor wafer, an irregularly shaped projec­tion on a semiconductor wafer surface with one or more irregu­larly developed facets. [ASTM F1241] Contrast pyramid. Also see haze.

mouse nip n - a semicircular intrusion into a straight edge of a film or etched pattern on a wafer or reticle. [SEMATECH] Also called mouse bite.