nick - see chip.
notch n 1 - an unexpected intrusion or reduction of linewidth in patterned geometries. May also be a V-shaped intrusion into the perimeter of a wafer. The intrusion is used to align the wafer during process. [SEMATECH] 2 - on a semiconductor wafer, an intentionally fabricated indent of specified shape and dimensions oriented such that the diameter passing through the center of the notch is parallel with a specified low index crystal direction. [SEMI M1-94 and ASTM F1241]
oil canning n - in metal lid/preform assembly, lid concavity after sealing. [SEMI G53-92]
overcoat - see passivation.
oxide defect n - an area of missing oxide on the back surface of back-sealed wafers discernible to the unaided eye. [ASTM F1241]
oxide etch n - an etch process in which unprotected areas of the oxide layer are eroded by use of a chemical to expose the underlying layer. [SEMATECH]
parametric test n - wafer-level testing of discrete devices such as transistors and resistors. [SEMATECH]
parasitic circuit element n - a circuit element that is an unavoidable adjunct of one or more other circuit elements
particle n 1 - a minute quantity of solid or liquid matter. [SEMATECH] 2 - in the manufacture of photolithographic pellicles, material that can be distinguished from the film, whether on the film surface or embedded in the film. [SEMI P5- 94] 3 - the replating step in which a catalytic material, often a palladium or gold compound, is absorbed on a surface to act as sites for initial stages of deposition. [ASTM B374-93]
particulate 1 n - discrete particle of dirt or other material. [ASTM F1241] 2 n (dust) - discrete particle of material that can usually be removed by (nonetching) cleaning. [SEMI M10- 89] 3 adj - describes material in small, discrete pieces; anything that is not a fiber and has an aspect ratio of less than 3 to 1. Examples are dusts, fumes, smokes, mists, and fogs. [SEMATECH]
particulate contamination n - on a semiconductor wafer, a particle or particles on the surface of the wafer. [ASTM F1241]
passivation n - deposition of a scratch-resistant material, such as silicon nitride and/or silicon dioxide, to prevent deterioration of electronic properties caused by water, ions, and other external contaminants. The final deposition layer in processing. [SEMATECH] Also called overcoat and cap deposition.
peeling n - any separation of a plated, vacuum deposited, or clad metal layer from the base metal of a leadframe, lead, pin, heatsink, or seal ring, from an underplate, or from a refractory metal on a ceramic package. Peeling exposes the underlying material. [SEMI G61-94] Also called flaking. Contrast blister metal.
peripheral chip n 1 - crystallographic damage along the circumference of a wafer. [SEMATECH] 2 - on a wafer surface, shallow crater formed in the periphery of the specimen through conchoidal fracture and resultant spalling. [ASTM F1241] Also called flake chip or surface chip.
pinhole n 1 - a minute defect or void in a film, mask, or resist, usually the result of contaminants. [SEMATECH] 2 - a small opening that extends through a covering, such as a resist coating or an oxide layer on a wafer. [SEMI P2-86]
pit n 1 - in a wafer surface, a depression in a wafer surface that has steeply sloped sides that meet the surface in a distinguishable manner, in contrast to the rounded sides of a dimple. [ASTM F1241] Also see slip and dislocation. 2 - in semiconductor packages, plastic or ceramic, or in the leadframes, a shallow depression or crater. The bottom of the depression must be visible in order for the term to apply. A pit is formed during the component manufacture. [SEMI G61-94] Contrast chip. 3 - in flat panel display substrates, a small indentation on the glass substrate surface. [SEMI D9-94]
point defect n - a localized crystal defect such as a lattice vacancy, interstitial atom, or substitutional impurity. [ASTM F1241] Contrast with localized light scatterer.
poly - see polycrystalline silicon.
polycrystalline adj - describes a form of semiconductor material made up of randomly oriented crystallites and containing large- angle grain boundaries, twin boundaries, or both. [SEMI M10-89 and ASTM F1241] Contrast single crystal. Also see amorphous silicon.
polycrystalline silicon (poly) n 1 - a nonporous form of silicon made up of randomly oriented crystallites or domains, including glassy or amorphous silicon layers. [ASTM F399-88] 2 - silicon formed by chemical vapor deposition from a silicon source gas or other methods and having a structure that contains large-angle grain boundaries, twin boundaries, or both. [SEMI M16-89] Also called poly and polysilicon. Contrast amorphous silicon and single crystal.
polysilicon (poly) - see polycrystalline silicon.
precipitate n 1 - within a silicon lattice, a region of silicon oxide frequently manifested as an etch pit. [ASTM F1241] Also see crystal lattice and pit. 2 - in a gallium arsenide wafer, a localized concentration of dopant that is insoluble. Precipitate is formed during crystal growth and during any process in which the temperature is sufficient to provide the necessary impurity mobility. [SEMI M10-89]
process-induced defect (PID) n - defect(s) added to the wafer as a result of a processing step. The PID wafer undergoes the same process sequence as a product wafer. PID wafer data is a closer approximation of actual process defect contributions than particles per wafer pass (PWP) wafer data. [SEMATECH]
pyramid n - a structure displaying |111| facets that appears on surfaces after epitaxial growth.
registration n 1 - the accuracy of the relative position of all functional patterns on any reticle with the corresponding patterns of any other reticle of a given device series when the reticles are properly superimposed. [ASTM F127-84] 2 - a vector quantity defined at every point on the wafer. It is the difference, R, between the vector position, P1 , of a substrate geometry and the vector position of the corresponding point, P0 , in a reference grid. [SEMATECH] 3 - in the overlay capabilities of wafer steppers, a vector quantity defined at every point on the wafer. It is the difference, R, between the vector position, P1, of a substrate geometry, and the vector position of the corresponding point, P0 , in a reference grid. [SEMI P18-92]
residue n - any undesirable material that remains on a substrate after any process step. [ASTM F127-84 and SEMI P3-90]
root cause n 1 - in failure analysis, the fundamental incident or condition that initially caused the failure to occur.
saucer pits - see shallow etch pits.
saw-blade defect n 1 - on semiconductor wafers, a roughened area visible after polishing with a pattern characteristic of the saw blade travel. [ASTM F1241] Also see saw marks. 2 - a depression in the wafer surface made by the blade, which may not be visible before polishing. [SEMI M10-89]
saw exit chip n - in gallium arsenide technology, an edge fragment on a wafer broken off at the point at which the saw completed its cut of the wafer. A saw exit chip is typically straight or arc shaped, not irregular, and sometimes can be confused with the orientation flats. [SEMI M10-89] Contrast saw exit mark.
saw exit mark n - in silicon technology, a ragged edge at the periphery of a wafer consisting of numerous adjacent small adjoining edge chips resulting from saw blade exit. [ASTM F1241] Also see saw marks, saw exit chip.
saw-kerf - see scribe line.
saw marks n - on a wafer, surface irregularities in the form of a series of alternating ridges and depressions in arcs, the radii of which are the same as those of the saw blade used for slicing. [ASTM F1241] Also see saw exit mark.
scanning electron microscope (SEM) n - a device that displays an electronically scanned image of a die or wafer for examination on a screen or for transfer onto photographic film; displays a higher magnification than an optical microscope. [SEMATECH]
scanning tunneling microscope (STM) n - an instrument for producing surface images with atomic scale lateral resolution, in which a fine probe tip is raster scanned over the surface and the resulting tunneling current is monitored. [SEMATECH]
scratch n - on semiconductor wafers, a shallow groove or cut below the established plane of the surface, with a length to width ratio greater than 5:1. [ASTM F1241] Also see macroscratch, microscratch.
Scribe line n - the area on a wafer between the individual die sites reserved for cutting the wafer into individual dice.
scum n - resist residue located in a window or along the foot of patterned geometry. [SEMATECH]
scumming n - residual resist located in areas that should have been cleaned in the develop operation. [SEMATECH]
SEM - see scanning electron microscope.
semiconductor n 1 - an element that has an electrical resistivity in the range between conductors (such as aluminum) and insulators (such as silicon dioxide). Integrated circuits are typically fabricated in semiconductor materials such as silicon, germanium, or gallium arsenide. [SEMATECH] 2- a material in which the electric current is made up of both negative and positive carriers (i.e., conduction electrons and holes, respectively) [JESD77].
shallow etch pits n - on a wafer, etch pits that are small and shallow in depth under high magnification greater than 200X. [ASTM F1241] Also called saucer pits. Also see haze.
short - see bridge.
silicon (Si) n - a brownish crystalline semimetal used to make the majority of semiconductor wafers. [SEMATECH]
silicon dioxide (SiO2 ) n - a passivation layer thermally grown or deposited on wafers. It is resistant to high temperatures. Oxygen or water vapor is used to grow silicon dioxide at temperatures above 900oC. Silicon dioxide is used as a masking layer as well as an insulator. [SEMATECH] Also called quartz. Also see glass.
silicon nitride (Si3 N4 ) (abbr. SiN) n - a passivation layer chemically deposited on a wafer at temperatures of between 600oC and 900oC to protect the wafer from contamination. Silicon nitride is also used as a masking layer and as an insulator. [SEMATECH]
silicon on insulator (SOI) n - a novel substrate for high-performance, low-power, and radiation-hard CMOS applications that offers process simplification, improved scalability, latch-up free and soft-error free operation, improved subthreshold slope, and drastic reduction in parasitic capacitances. At this writing, there are two manufacturing-oriented techniques to build SOI: SIMOX and bonded. Also see SIMOX and bonded. [SEMATECH]
slice - see wafer.
slip n - in semiconductor wafers, a process of plastic deformation in which one part of a crystal undergoes a shear displacement relative to another in a manner that preserves the crystallinity of each part of the material. DISCUSSION—After preferential etching, slip lines are evidenced by a pattern of one or more parallel straight lines of dislocation etch pits that do not necessarily touch each other. On |111| surface, group of lines are inclined at 60o to each other; on |100| surfaces, they are inclined at 90o to each other. [SEMI M10-89 and ASTM F1241] Also see pit.
slip line n - a step occurring at the intersection of a slip plane with the surface. [ASTM F1241]
slip plane n - the crystallographic plane on which the dislocations forming the slip move. [ASTM F1241]
small scale integration (SSI) n - the placement of between 2 and 10 active devices on a single die. [SEMATECH] Also see die.
smudge n - a dense local area of contamination usually caused by handling or fingerprints. [SEMI M1-94 and ASTM F1241]
snowball n - on a semiconductor wafer, a track with the appearance under magnification of a snowball rolled through snow. [ASTM F1241]
SOI - see silicon on insulator.
source 1 n - one of the three major components of a CMOS transistor. [SEMATECH] 2 n - a supply region that supplies principal-current charge carriers into a controlled channel [JESD77]
spike n 1 - on an epitaxial wafer surface, a tall, thin dendrite or crystalline filament that often occurs at the center or recess. [ASTM F1241] 2 - an extreme structure that has a large ratio of height-to- base width and no apparent relation to epitaxial film thickness. [SEMATECH] Also see pyramid and mound.
SSI - see small scale integration.
stacking fault n - in a crystal, a two-dimensional defect caused by a deviation from the normal stacking sequence of atoms. [ASTM F1241]
stain n 1 - a solution applied to a cross-sectioned silicon device to reveal the location of various structures. [SEMATECH] 2 - contaminant in the form of streaks that are chemical in nature and cannot be removed except through further lapping or polishing. Examples are “white” stains that are seen after chemical etching as white or brown streaks. [SEMI Materials, Vol. 3, Definitions for Semiconductor Materials] 3 - a two-dimensional, contaminating foreign substance on a component surface. [SEMATECH] Also see contamination and foreign material. 4 - in flat panel display substrates, any erosion of the surface; generally cloudy in appearance, it sometimes exhibits apparent color. [SEMI D9-94] 5 - area contamination that is chemical in nature and cannot be removed except through further lapping or polishing. [ASTM F1241]
step coverage n - the ratio of thickness of film along the walls of a step to the thickness of the film at the bottom of a step. Good step coverage reduces electromigration and high-resistance pathways. [SEMATECH]
STM - see scanning tunneling microscope.
stuck-at fault n - a fault in a manufactured circuit causing an electrical node to be stuck at a logical value of 1 or a logic value of 0, independent of the input to the circuit. [1994 National Technology Roadmap for Semiconductors]
substrate n - in the manufacture of semiconductors, a wafer that is the basis for subsequent processing operations in the fabrication of semiconductor devices or circuits. [ASTM F1241]
surface chip - see peripheral chip.
surface defects n 1 - in the manufacture of silicon on sapphire (SOS) epitaxial silicon wafers, mechanical imperfections, SiO2 residual dust, and other imperfections visible on the wafer surface. Some examples of surface defects are: dimples, pits, particulates, spots, scratches, smears, hillocks, and polycrystalline regions. [SEMI M4-88] 2 - in flat panel display substrates, a marking, tearing or single line abrasion on the glass surface. [SEMI D9-94]