Terms T-Z

T

tester pattern generation (TPG) n - the generation of a program that runs on an integrated circuit hardware tester (integrated cir­cuit tester). The purpose of this program is to permit test vectors to be applied to the pins of the integrated circuit, and measure­ments made to determine the performance of the integrated cir­cuit. [1994 National Technology Roadmap for Semiconductors] Also called tester program generation.

test pattern - see pattern, test.

test techniques n - any methods used for the expressed purpose of testing integrated circuits. Examples include built-in self test (BIST), automatic test pattern generator (ATPG), static current test (IDDQ ), and boundary scan. [1994 National Technology Roadmap for Semiconductors]

test vectors n - sequences of signals applied to the pins of an inte­grated circuit to determine whether the integrated circuit is per­forming as it was designed. [1994 National Technology Roadmap for Semiconductors]

total reflection X-ray fluorescence (TXRF) n - an analytical method usually used to characterize the level of metallic (and nonmetallic elemental) surface contamination. In TXRF, an X- ray beam excites fluorescence from the contamination that is present on a silicon surface. Since the beam is incident at grazing angles, it totally reflects from the surface, thus maximizing the signal. [SEMATECH]

trapped charges n - charges trapped either in the gate oxide or, in the case of a lightly doped drain (LDD) metal-oxide semicon­ductor field-effect transistor (MOSFET), in the spacer region. Trapped charges in the gate or the spacer lead to threshold volt­age shift or to transconductance degradation, respectively. [SEMATECH]

TXRF - see total reflection X-ray fluorescence.

U

ULSI - see Ultra Large Scale Integration

Ultra large Scale Integration - the placement of at least 1,000,000 active devices on a single die. [JESD99]

undercutting n - the lateral etching into a substrate under a resistant coating, as at the edge of a resist image. [ASTM F127-84]

unencapsulated thermal test chip n - an unpackaged, specially designed silicon die with standard test junctions that, after mounting into a package, may be used to thermally characterize that package. This technique is useful in determining the differ­ence between various vendors’ packages and package designs. [SEMATECH]

V

Very Large Scale Integration - n the placement of at least 1000 active devices on a single die. [JESD99]

via n 1 - a connection between two conducting layers above the silicon surface that is created by a different material or deposition step.

VLSI - see Very Large Scale Integration

void 1 - see dielectric void. 2 - see glass void. 3 - see metallization void.

W

wafer n - in semiconductor technology, a thin slice with parallel faces cut from a semiconductor crystal. [ASTM F1241] Also called a slice. Also see substrate.

well n - a localized n-type region on a p-type wafer or a p-type region on an n-type wafer. [SEMATECH]

X

X-ray fluorescence n 1 - the property of atoms to absorb X rays and emit light of characteristic wavelengths. [SEMATECH] 2 - a material diagnostic technique that determines the surface con­centration of contaminants. [SEMATECH]

Y

(none)

Z

(none)