Design Debug is an increasingly difficult and complex process. Today, engineers are required to locate design problems and process variation points on complex integrated circuits. In many ways, this is akin to locating a needle in a haystack, where the needles get smaller and the haystack gets bigger every year. Engineers are required to understand a variety of disciplines in order to effectively perform design debug. This requires knowledge of design, testing, technology, and even processing. Non-functional, partially functional devices, and low yields can lead to product introduction delays and idle manufacturing lines that can cost a company millions of dollars per day. Our industry needs competent analysts to help solve these problems.
Design Debug is a 3-day course that offers detailed instruction on a variety of effective tools, as well as the overall process flow for locating and characterizing the design and/or manufacturing problem responsible for the failure. This course is designed for every manager, engineer, and technician working in the semiconductor field, designing complex integrated circuits, or supplying tools to the industry.
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Please note: If you or your company plan to pay by wire transfer, you will be charged a wire transfer fee of USD 45.00.
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If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.
Participants will learn how to determine what tools and techniques should be applied and when they should be applied. This skill-building series is divided into three segments:
By using a combination of instruction by lecture, exercises, and question/answer sessions, participants will learn practical approaches to the design debug process. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. Our instructors are internationally recognized experts in their fields and possess years of current and relevant experience.
Gary Woods has been involved in the semiconductor and optics fields for 18 years. He graduated from Rice University in 1988 with a B.S.E.E. and B.A. (physics). After graduating from Rice University, he spent two summers at Texas Instruments developing advanced electron-beam voltage-probing instruments. He then attended Stanford University and obtained his Ph.D. in Applied Physics in 1997. His Ph.D. research centered on mid-IR nonlinear optical interactions in semiconductor quantum wells. From 1996-1998 he worked on quantum-well and nonlinear-optical physics as a postdoctoral researcher in the ECE department at the University of California, Santa Barbara. He joined Intel Corp. in 1998, where he worked on development of high-bandwidth optical probing techniques, including the Laser Voltage Probe, Time-Resolved Emission, and Dynamic Laser Stimulation. From 2000-2002 he was the CTO of a venture-funded startup company, which he co-founded, manufacturing fiber-optical equipment. From 2003-2006 he was a Senior Scientist at Credence Systems Corp.’s Diagnostics and Characterization group. His contributions included developing advanced measurement techniques using time-resolved emission and developing new laser-based probing technologies. He also provided applications support for several Credence customers’ debug efforts. He is now with Sooner Silicon Consulting Services. He holds 8 U.S. patents and has authored or co-authored more than 30 peer-reviewed publications, including more than 20 publications in the field of optical probing of silicon circuits.
Dr. Michael Bruce received a BS and PhD in Physics from the University of Texas at Austin. After a post-doc at Indiana University, he joined Advanced MicroDevices, Inc. in 1995. He now has over 15 years experience in failure analysis and design debug of microprocessors. He helped pioneer the backside failure analysis field with development of optical techniques like RIL/SDL and single-element Time Resolved Emission. Mike holds 74 patents and has published numerous papers related to failure analysis and design debug, including a best paper and outstanding paper at ISTFA for RIL and SDL, respectively. He has chaired and given many tutorials at IRPS, ISTFA, and IPFA, as well given many lectures at Universities and technical seminars. Mike currently works as an independent consultant helping customers understand and implement new FA technologies.