The drive to reduce costs in semiconductor and integrated circuits remains a key challenge for the industry. For example, many of today's ICs use expensive gold wiring. As a result, the industry is pushing to use copper wires and copper pillar bumping in an increasing array of applications. This has created a number of challenges related to the bonding and packaging of these components. Copper Wire Bonding Technology and Challenges is a 2-day course that offers detailed instruction on the technology issues associated with today's semiconductor packages. We place special emphasis on current issues like bond formation, bumping, and tools for package analysis. This course is a must for every manager, engineer, and technician working in semiconductor packaging, using semiconductor components in high performance applications or non-standard packaging configurations, or supplying packaging tools to the industry.
By focusing on current issues in packaging technology, participants will learn why advances in the industry are occurring along certain lines and not others. Our instructors work hard to explain semiconductor packaging without delving heavily into the complex physics and materials science that normally accompany this discipline.
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Please note: If you or your company plan to pay by wire transfer, you will be charged a wire transfer fee of USD 45.00.
Please email the printable registration form for public courses to us at the email address on the form to complete your order.
Participants learn basic but powerful aspects about semiconductor packaging. This skill-building series is divided into four segments:
By using a combination of instruction by lecture, classroom exercises, and question/answer sessions, participants will learn practical information on semiconductor packaging and the operation of this industry. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field.
Steve Groothuis received a Bachelor's in Physics (1983) from Michigan State University and Masters in Physics (1991) from the University of Texas. He began performing semiconductor package development, design, testing, and simulation in the Central Packaging Group, Texas Instruments in Dallas in 1983 as a Group Member of the Technical Staff. Prior to leaving TI, he managed the engineering staff in TI's Advanced Semiconductor Packaging Lab. In 1997, he was a Multiphysics Industry Specialist for ANSYS, Inc., defining Computer-Aided Engineering simulation software market plans, strategic accounts management, electronics packaging, MEMS device simulation initiatives, and product development for the electronics industry. From 2000-2008, he was with Micron Technology in positions from Senior Package Engineer in the Assembly and Packaging Department to Technology CAD and Analysis Manager in the Process RD Department at Micron Technology. His responsibilities included working with device and process simulations for new cell designs, supporting most aspects of semiconductor package simulations, and assessing new technology.
Currently, Mr. Groothuis is a Principal Consulting Engineer with SimuTech Group, Inc. He is actively involved in developing and winning new business opportunities for Finite Element Analysis (FEA) and Computational Fluid Dynamics (CFD) consulting projects. His efforts are focused on vertical markets such as Microelectronics, Semiconductor Packaging, Wafer Fabrication, NEMS/MEMS, Nanotechnology, Solar Energy, Wind Energy, and Consumer Electronics.
He has published over 30 papers at various conferences in semiconductor packaging, reliability, and numerical analysis. Mr. Groothuis is a Senior Member of the IEEE and has participated in ASME and JEDEC standards committees.