As component sizes shrink, packaging is coming to the forefront as a key challenge the semiconductor industry faces in the 21st century. IC Packaging Metallurgy is a 2-day course that offers detailed instruction on the metallurgy issues associated with today's semiconductor packages.
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Please note: If you or your company plan to pay by wire transfer, you will be charged a wire transfer fee of USD 45.00.
Please email the printable registration form for public courses to us at the email address on the form to complete your order.
This skill-building series is divided into four segments:
This course is a must for every engineer and technician with limited materials science training or experience. The course can also serve as a targeted review for materials scientists with limited experience in IC packaging assembly. Our instructors work hard to explain semiconductor packaging without delving heavily into the complex physics and materials science that normally accompany this discipline.
Our courses are dynamic. We use a combination of instruction by lecture, problem solving, and question/answer sessions to give you the tools you need to excel. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. The course notes offer hundreds of pages of reference material that participants can apply during their daily activities.
Our instructors are internationally recognized experts. Our instructors have years of current and relevant experience in their fields. They're focused on answering your questions and teaching you what you need to know.
Dr. Roger Stierman is an independent consultant who focuses on packaging issues and analysis techniques. Roger received a B.S. in Physics from Loras College and M.S. and Ph.D. degrees in Metallurgy from Iowa State University. During his 25-year career at Texas Instruments, he developed processes for semiconductor package assembly and characterized semiconductor packaging materials such as die attach, mold compounds, polymer overcoats, wire bond and flip chip connections, flip chip underfills, and package-to-PWB attachment. As manager of the Semiconductor Packaging Lab, he delivered training for physical failure analysis methods including precision cross-sectioning, SEM/EDS, X-Ray, tensile and 4-point bend testing, microhardness, RIE/ICP etching, ion milling and laser decapsulation. Currently, he is a consultant on semiconductor packaging failure analysis for Omniprobe, Inc.