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Interconnect Process Integration

Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today's chips contain hundreds of millions of transistors. These challenges have been accomplished because of the integrated circuit industry's ability to track Moore's Law. This has been accomplished by making devices smaller and smaller. However, the interconnect metals and associated dielectric materials that facilitate wiring between the transistors are severely limiting further performance improvements. Scientists and engineers are scrambling for materials that can allow performance improvements without sacrificing cost and reliability. Interconnect Process Integration is a 1-day course that offers detailed instruction on the materials, processing technologies, and integration necessary to create high performance interconnect systems. We place special emphasis on current issues related to designing and manufacturing of next-generation devices. This course is a must for every manager, engineer, and technician working in the semiconductor industry, using semiconductor components, or supplying tools to the industry.

By focusing on the fundamentals of interconnect performance, participants will learn why advances in the industry are occurring along certain lines and not others. Our instructors work hard to explain how interconnect systems work without delving heavily into the complex chemistry and materials science that normally accompany this discipline.

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Refund Policy

If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

What Will I Learn By Taking This Class?

Participants learn basic but powerful aspects about the semiconductor industry. This skill-building series is divided into three segments:

  1. Basic Device Operation. Participants learn the fundamentals of interconnect performance. They learn why the industry is in a state of flux regarding backend metal and dielectric systems.
  2. Fabrication Technologies. Participants learn the fundamental manufacturing technologies used to make modern interconnect systems. They learn the typical process flows used in metal and dielectric deposition, as well as polishing, etch stop techniques, hard masks, and more.
  3. Current Issues in Process Integration. Participants learn how interconnect performance is increasingly constrained by resistance and capacitance. They also learn about the impact of using new materials in the fabrication process and how those materials may create problems for the manufacturers in the future.
  4. An Overview of Issues Related to Process Integration. Participants learn about the image of new materials, yield, reliability, and scaling on interconnect integration. They receive an overview of the major reliability mechanisms that affect interconnect systems today.

Course Objectives

  1. The seminar will provide participants with an in-depth understanding of the semiconductor industry and its technical issues.
  2. Participants will understand the basic concepts behind interconnect performance.
  3. The seminar will identify the key issues related to the continued growth of the semiconductor industry.
  4. The seminar offers a wide variety of sample problems that participants work to help them gain knowledge of the fundamentals of backend manufacturing.
  5. Participants will be able to identify basic and advanced technology features on semiconductor devices. This includes features like copper, barrier layers, etch stop layers, and a variety of low-k dielectrics.
  6. Participants will understand how reliability, power consumption and device performance are interrelated.
  7. Participants will be able to make decisions about how to construct and evaluate new backend processes.

Course Outline

Day 1

  1. Introduction
    1. Interconnect scaling
  2. Low-k Materials
    1. What is k?
    2. Low-k; organic vs inorganic
    3. Porosity
    4. Barrier layers; SiN; SiC
    5. Electrical properties
    6. Mechanical properties
    7. Thermal properties
    8. Thermal and Chemical stability
  3. Integration of Cu with Low-k Materials
    1. Integration options
    2. Effective k
    3. Patterning
    4. Cleans
    5. Metal deposition
    6. CMP
    7. Packaging
  4. Reliability of Cu interconnects in low-k materials
    1. Electromigration
    2. Stress migration
    3. Oxidation
    4. TDDB
    5. Package reliability
    6. Intrinsic vs extrinsic fails

Instructional Strategy

By using a combination of instruction by lecture, classroom exercises, and question/answer sessions, participants will learn practical information on semiconductor devices and the operation of this industry. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. Our instructors are internationally recognized experts in their fields and have years of both current and relevant experience.The course notes offer many pages of additional reference material the participants can use back at their daily activities.

Instructor Profile

Dr. Jeffrey Gambino

Jeffrey Gambino

Dr. Gambino received his B.S. degree in materials science from Cornell University, Ithaca, NY, in 1979, and his Ph.D. degree in materials science from the Massachusetts Institute of Technology, Cambridge, MA, in 1984. He joined IBM, Hopewell Junction, NY, in 1984, where he worked on silicide processes for Bipolar and CMOS devices. In 1992, he joined the DRAM development alliance at IBM's Advanced Semiconductor Technology Center, Hopewell Junction, NY. While there, he developed contact and interconnect processes for 0.25-, 0.175-, and 0.15-mm DRAM products. In 1999, he joined IBM's manufacturing organization in Essex Junction, VT, where he has worked on copper interconnect processes for CMOS logic technology. He has published over 90 technical papers and holds over 100 patents.