Design for Reliability

Semiconductor reliability is at a crossroads. In the past, reliability meant discovering, characterizing, and modeling failure mechanisms and determining their impact on the reliability of the circuit. Today, reliability can involve tradeoffs between performance and reliability, assessing the impact of new materials, dealing with limited margins, etc. The product lifecycle for many components has become so short that there are limited opportunities to impact the overall reliability of the device, whether that be testing at the package level or even the wafer level. While reliability levels are at an all-time high level in the industry, design changes and tradeoffs may cause the chip reliability to quickly deteriorate. Thus, engineers have to put thought and effort into the reliability of a component during the design phase.

How can you do this properly? Your company needs competent engineers and scientists to help solve these problems. Semitracks' 3-day Design for Reliability course offers detailed instruction on a variety of subjects pertaining to designing in reliability.

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Refund Policy

If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

What Will I Learn By Taking This Class?

The course is divided into three segments:

  1. Fundamentals of Reliability Physics and Accelerated Testing. Participants learn the fundamentals of various failure mechanisms and the testing used to accelerate those mechanisms.
  2. Design-In Reliability Issues. Participants learn how the major failure mechanisms manifest themselves at the circuit and chip level. These include: time-dependent dielectric breakdown, hot carrier degradation, electromigration, stress-induced voiding, moisture, corrosion, contamination, thermomechanical effects, etc. They learn the process for converting test structure results into circuit level behaviors.
  3. Mission Profiles. Participants learn the conversion of transient use-conditions into static equivalents for Design Rule generation and verification.

The course is designed for every manager, engineer, and technician concerned with reliability in the semiconductor field, designing semiconductor components, or supplying tools to the industry.

Course Objectives

  1. The seminar will provide participants with an in-depth understanding of the failure mechanisms, test structures, equipment, and testing methods used to achieve today's high reliability components.
  2. Participants will be able to identify basic test structures and how they are used to help quantify reliability on semiconductor devices.
  3. Participants will be able to interpret test structure data and make inferences from that data.
  4. The seminar will identify the major failure mechanisms, explain how they are observed, and how they are modeled at the circuit level.
  5. Participants will learn to convert dynamic condition test data into a static model that can be used in the design environment for design rule checking and layout.
  6. Participants will be able to knowledgeably implement screens that are appropriate to assure the reliability of a component.
  7. Participants will be able to identify appropriate software tools to purchase when starting or expanding their design operations.

Instructional Strategy

Our courses are dynamic. We use a combination of instruction by lecture, problem solving, and question/answer sessions to give you the tools you need to excel in semiconductor reliability design. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. The course notes offer hundreds of pages of reference material that the participants can apply during their daily activities.

Our instructors are internationally recognized experts. Our instructors have years of current and relevant experience in their fields. They're focused on answering your questions and teaching you what you need to know.

Instructor Profile

Dr. Joe McPherson

Dr. Joe McPherson received his Ph.D. in Physics from Florida State University. Prior to joining Texas Instruments, he was an assistant professor with the University of North Carolina and a visiting scientist with the Argonne National Laboratory. He joined TI in 1980 as a process development engineer and was instrumental in bringing silicides and laser redundancy into IC production. Since 1983, he has primarily focused on reliability physics, where he has received numerous Best/Outstanding Paper Awards, published over 200 articles on semiconductor reliability, authored the reliability chapters for four books, and holds 12 patents. He was the 1995 general chairman of the IEEE International Reliability Physics Symposium (IRPS) and still serves on its board of directors. In 2004, Joe received the IEEE Engineer of the Year Award from the Texas Society of Professional Engineers. In 2006, he was chairman of the Sematech Reliability Council. Joe is Texas Instruments' Senior Fellow Emeritus and an IEEE Fellow.