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Dynamic Random Access Memory

Dynamic Random Access Memory is key to many electronic systems. The density and performance make it the memory of choice for many systems, including personal computers, workstations, embedded computing, game consoles, and more. As memory performance increases, the number of DRAM architectures and options available increase. Electronic system designers need to understand the options for integrating these memories into their systems and how to test them to ensure proper operation. Furthermore, many companies are beginning to offer embedded DRAM for use in System-on-a-Chip (SoC) applications. In these devices, testing becomes even more of a challenge. DRAM Design, Technology and Testing is an intensive 1-day course designed to provide this understanding to system-level designers, test engineers, product engineers, SOC system designers that plan to or are considering using embedded DRAM technology, and other individuals dealing with DRAM technology. Our instructor is an expert in the area of DRAM Design and Testing, and has spent more than a decade working specifically on these devices. He is uniquely qualified to give you and understanding of the issues associated with DRAM.

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If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

Course Outline

  1. Introduction to DRAM Design
    1. DRAM Block Diagrams
    2. DRAM Design Components: Array and Periphery
    3. DRAM Array Layout Components
    4. Embedded DRAM
  2. DRAM External and Internal Operation
    1. Data sheet
    2. Operation states
    3. Internal test setup
    4. Activation and Refresh operation
    5. Read operation
    6. Write operation
  3. Array Test Patterns
    1. Functional Tests – Write/Read and March
    2. Retention tests
    3. Disturb tests
    4. Leakage tests
    5. Signal Margin test
    6. Internal Timing Tests
  4. Array Diagnostics (Bitmapping) and DRAM Technology
    1. Chip Maps, Wafer Maps, Lot Maps
    2. Single Cell Fail Analysis Example
    3. Paired Cell – Cell to Cell Leakage Example
  5. Limits of Bitmapping
    1. Block Fail and Analysis
    2. Decoder Failure Analysis
    3. Redundancy Fail and Analysis
    4. Failure Analysis Techniques: Soft Defect Localization for DRAM
    5. Defect Modeling and Simulation
  6. Periphery: Operation Mode and Output Timing Tests
    1. Functional Tests
    2. Memory Tester Performance
    3. Measurement of Device Performance
    4. Timing Measurement Correlation
  7. Test Flow and Characterization
    1. Manufacturing Test Flow
    2. Shmoo
    3. Searches

Instructor Profile

Martin Versen, Ph.D.

Martin Versen

Martin Versen studied physics at the Ruhr-University Bochum, Germany and received his PhD in 2000 in electrical engineering for his work on single electron devices based on InAs quantum dots. He joined Qimonda's mother company, Infineon Technologies, in 2000 as product engineer in Munich, Germany, and Williston, VT being responsible for test coverage and customer return analysis in the commodity memory department. He was a senior staff engineer product and test and team leader of the root-cause analysis team in Munich from 2005 to 2009. Since 2009 he has been a professor of Engineering Sciences at The Rosenheim University of Applied Sciences.