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Defect-Based Testing

Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today's application-specific ICs and microprocessors can contain upwards of 100 million transistors. Traditional testing relies on the stuck-at-fault (SAF) to model defect behavior. Unfortunately, the SAF model is a poor model for defects. Other models and strategies are required to catch killer defects on integrated circuits. As transistor sizes decrease, the types and properties of the killer defects change. This has created a number of challenges related to the testing of components. Defect-Based Testing is a 2-day course that offers detailed instruction on the electrical behavior and test strategies for integrated circuits. We place special emphasis on electrical behavior, fault models, and test techniques. This course is a must for every manager, engineer, and technician working in IC test, IC design, or supplying test hardware and software tools to the industry.

By focusing on the fundamentals of circuit behavior and the impact of defects on circuit behavior, participants will learn how to design, write, and implement test strategies to catch defects. Our instructors work hard to explain semiconductor test without delving heavily into the complex algorithms and computer science that normally accompany this discipline.

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Course Dates | Location

November 18-19, 2024 | Munich, Germany

(Price available until Mon. Oct. 28)




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Please note: If you or your company plan to pay by wire transfer, you will be charged a wire transfer fee of USD 45.00.

Please email the printable registration form for public courses to us at the email address on the form to complete your order.

Additional Information

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Refund Policy

If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

What Will I Learn By Taking This Class?

Participants will learn basic, but powerful, aspects about defect-based testing. This skill-building series is divided into four segments:

  1. Electrical Behavior of Defects. Participants will study the electrical behavior of defects. They will learn how open circuits, resistive vias, shorts, and transistor variations affect the electrical behavior of the individual transistor, as well as gate elements and larger blocks.
  2. Fault Models for Defect-Based Testing. Participants will learn about the historical underpinnings of the stuck-at-fault (SAF) model. They will also learn about other testing models, including IDDQ testing, at-speed testing, and delay testing.
  3. Production Test Methods. Participants will learn about standard digital testing, SAF testing, IDDQ, timing, low voltage tests, and other types of stress tests. They will explore the strengths and weaknesses of each test type.
  4. The Economic and Quality Impact of Defect-Based Testing. Participants will learn how defect-based testing can actually improve test economics. They will also study the impact on quality and reliability.

Course Objectives

  1. The course will provide participants with an in-depth understanding of defect-based testing and its technical issues.
  2. Participants will understand the basic concepts of test economics, yield, test time, and the cost of test. They will also learn how defect-based testing can reduce the possibility of failures in the field.
  3. The course will identify underused test techniques like IDDQ and Very Low Voltage (VLV) test techniques that can successfully find defects that are difficult to catch using conventional test techniques.
  4. The course will offer the opportunity to discuss specific test problems with our expert instructors.
  5. Participants will be able to identify basic and advanced principles for defect-based test.
  6. Participants will understand the difficulties in extending IDDQ testing to leading edge products, and how to overcome some of these limitations.
  7. Participants will become familiar with Design for Test (DFT) and Automatic Test Pattern Generation (ATPG) tools used for defect-based testing.
  8. The course will introduce fundamental and advanced concepts related to extending defect-based testing to future designs.
  9. Participants will learn what tools are available today to implement defect-based testing.

Course Outline


  1. What is Defect-Based Testing?
    1. Introduction
    2. Terminology
    3. Existing test techniques
  2. CMOS IC Defect Mechanisms and Detection Techniques
    1. Normal transistor and gate behavior
    2. Sources of random and systematic defects
    3. Types of Defects and How to Detect Them
      1. Bridging defects
      2. Resistive defects
      3. Open circuit defects
      4. Delay defects
  3. Fault Models for Defect-Based Test
    1. Stuck-at-fault (SAF)
    2. Delay fault

Day 2

  1. Fault Models for Defect-Based Test
    1. Leakage fault
    2. Methods for implementing fault models
    3. Existing software tools
  2. Production Test Methods
    1. Functional testing (At-speed testing)
    2. IDDx Testing
    3. Timing Test
    4. Low Voltage Testing
    5. Stress Testing
  3. Defect-Oriented test Economics and Product Quality
    1. Test set reduction
    2. Effectiveness in catching defects
    3. Yield and fallout
  4. Case Histories

Instructional Strategy

Our courses are dynamic. We use a combination of instruction by lecture, problem solving, and question/answer sessions to give you the tools you need to excel in the defect-based testing process. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. The course notes offer hundreds of pages of reference material that you can reference and apply during your daily activities.

Our instructors are internationally recognized experts. Our instructors have years of current and relevant experience in their fields. They're focused on answering your questions and teaching you what you need to know.

Instructor Profiles

Christopher Henderson, President of Semitracks

Christopher Henderson

Christopher Henderson received his B.S. in Physics from the New Mexico Institute of Mining and Technology and his M.S.E.E. from the University of New Mexico. Chris is the President and one of the founders of Semitracks Inc., a United States-based company that provides education and semiconductor training to the electronics industry.

From 1988 to 2004, Chris worked at Sandia National Laboratories, where he was a Principal Member of Technical Staff in the Failure Analysis Department and Microsystems Partnerships Department. His job responsibilities have included failure and yield analysis of components fabricated at Sandia's Microelectronics Development Laboratory, research into the electrical behavior of defects, and consulting on microelectronics issues for the DoD. He has published over 20 papers at various conferences in semiconductor processing, reliability, failure analysis, and test. He has received two R&D 100 awards and two best paper awards. Prior to working at Sandia, Chris worked for Honeywell, BF Goodrich Aerospace, and Intel. Chris is a member of IEEE and EDFAS (the Electron Device Failure Analysis Society).

At Semitracks, Chris teaches courses on failure and yield analysis, semiconductor reliability, and other aspects of semiconductor technology.

Michael Bruce, Ph.D.

Dr. Michael Bruce received a B.S. and Ph.D. in Physics from the University of Texas at Austin. After a post-doctoral at Indiana University, he joined Advanced MicroDevices, Inc. in 1995. He now has over 15 years experience in failure analysis and design debug of microprocessors. He helped pioneer the backside failure analysis field with development of optical techniques like RIL/SDL and single-element Time Resolved Emission. Dr. Bruce holds 74 patents and has published numerous papers related to failure analysis and design debug, including a best paper and an outstanding paper at ISTFA for RIL and SDL, respectively. He has chaired and given many tutorials at IRPS, ISTFA, and IPFA, as well as given many lectures at universities and technical seminars. He currently works as an independent consultant, helping customers understand and implement new FA technologies.

Robert Aitken, Ph.D.

Robert Aitken

Dr. Aitken has spent the last 15 years working on various aspects of IC design for testability. His current responsibilities include design and test methodology for Artisan's Libraries (Artisan is now a part of ARM Ltd). He has worked in a variety of areas relating to test, including test synthesis, fault modeling, IDDQ testing, and fault diagnosis, as well as contributing to numerous proprietary and/or patented technologies for Agilent's IC business. Additionally, Dr. Aitken has published over 40 technical papers on testing and diagnosis and received the best paper award from the International Test Conference in 1992. He holds a Ph.D. from McGill University in Canada. In addition to being a member of the IEEE and an associate editor of IEEE Transactions on Computer-Aided Design, Dr. Aitken serves on several program committees, including that of International Test Conference. He has also served on the executive committee of the International Conference on CAD and the International Test Synthesis Workshop.