System Maintenance occurs every Friday.
During a semiconductor product life cycle there’s a launch into high volume production test - key aspects include devising a test strategy & flow - that provides sufficient test coverage to meet customer requirements yet still meet cost targets. Design and test are closely linked and there’s a push to always implement test during the design process, known as "shift left", to determine what can be designed into the chip to fit seamlessly with test flows/outcomes. Products are typically guaranteed to meet performance through three aspects - testing, characterization, and the very design itself. The strategy involves selecting automated test equipment (ATE) along with wafer probers and packaged part handlers. There are many nuances to wafer probers and handlers depending on the wafer type and the package. There may also be ongoing accelerated life testing (burn-in) and system level test (SLT). Many applications require testing across temperature and thermal management of dissipated power. All product lifecycles need to include continuous improvements to the point of diminishing return (known as the "Kaizen" philosophy). For test this is typically test cost reduction and test coverage improvement. All of this is combined with test programs (software) and test hardware beyond the basic tester, handler, and prober. Testing generates extremely high volumes of data, so the key is how to harvest this data and reduce it to meaningful information for action.
January 29-30, 2024 | Phoenix, AZ, USA
Please note: If you or your company plan to pay by wire transfer, you will be charged a wire transfer fee of USD 45.00.
Please email the printable registration form for public courses to us at the email address on the form to complete your order.
The course will cover the basic segments of today’s high volume production test - found in Outsourced Assembly And Test contractors (OSATs), as well as internal Integrated Device Manufacturers (IDMs). Participants will gain an understanding of:
Test flows, strategy and equipment need to be optimized for the application - there are many significant differences / needs across device types
Product lifecycle & test
Mark Berry is an independent consultant assisting startups in reducing the cost of test, implementing test strategies, accelerating new product introduction, and assisting test operations and business development. He also represents several test hardware, tester and test development firms. He has a deep understanding of high-volume semiconductor test.
His past roles have included process and device engineering roles at Motorola and Freescale. While at Motorola/Freescale, he was granted three device patents and authored several papers. He received the CEO Quality Award for radical improvements to FSRAM yield and reliability. This led to the Motorola’s first perfect 100% yielding wafer. He led large product and test operation teams across a wide spectrum of chips used in cellular phone applications – leading to 25 transceiver product qualifications across 7 technologies. His efforts helped to improve gross margins by 20%. Specifically, in the RF Power Amplifier module area, his efforts helped achieve a 60% cost reduction in 6 months. He is adept at taking products through concept, selection, definition, planning, execution, validation & ramp. Mark also sponsored a number of rotational engineers and enjoys teaching & mentoring.
He has also held executive leadership roles during his 14-year tenure at Amkor, leading worldwide test development across three sites. He maintained and implemented Amkor’s test equipment roadmap and regional test business development activities. He led global teams to implement complex advanced packaging flows (2.0/2.5/3D technologies) and devise optimum test flows for them. Finally, he worked at UTAC, leading their US business development team. He is familiar with a broad range of ATE & SLT testers, many types of handlers and probers, as well as contacting via probe cards and a wide variety of socket technology.
Mark has an MBA from St Edward’s University and a BSEE from the University of Illinois at Urbana-Champaign.