System Maintenance occurs every Friday.

Fundamentals of High-Volume Production Test

During a semiconductor product life cycle there’s a launch into high volume production test - key aspects include devising a test strategy & flow - that provides sufficient test coverage to meet customer requirements yet still meet cost targets. Design and test are closely linked and there’s a push to always implement test during the design process, known as "shift left", to determine what can be designed into the chip to fit seamlessly with test flows/outcomes. Products are typically guaranteed to meet performance through three aspects - testing, characterization, and the very design itself. The strategy involves selecting automated test equipment (ATE) along with wafer probers and packaged part handlers. There are many nuances to wafer probers and handlers depending on the wafer type and the package. There may also be ongoing accelerated life testing (burn-in) and system level test (SLT). Many applications require testing across temperature and thermal management of dissipated power. All product lifecycles need to include continuous improvements to the point of diminishing return (known as the "Kaizen" philosophy). For test this is typically test cost reduction and test coverage improvement. All of this is combined with test programs (software) and test hardware beyond the basic tester, handler, and prober. Testing generates extremely high volumes of data, so the key is how to harvest this data and reduce it to meaningful information for action.

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Course Dates | Location

January 29-30, 2024 | Phoenix, AZ, USA



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If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

Course Objectives

The course will cover the basic segments of today’s high volume production test - found in Outsourced Assembly And Test contractors (OSATs), as well as internal Integrated Device Manufacturers (IDMs). Participants will gain an understanding of:

  1. Higher understanding of role & importance of test and "shift left" design linkage.
  2. Test by application / market segment.
  3. Basic test segments and sequences across the fab/bump/probe/test flow.
  4. Types of test and outcomes / actions taken.
  5. Next steps after test.
  6. Test systems, material handling and contacting.
  7. Reducing data to actionable information.
  8. Continuous improvement over product lifecycle.
  9. Trends in test and future of.

Course Outline

Section 1 Why Test? Necessary evil? Non-value-added activity? Or is there more to it?

  1. Why test?
  2. What aspects are value added and non-value added (necessary evil?)
  3. Basic drivers include isolating defective parts, triggering repair algorithms, product binning - example fast parts with shorter battery life or slow parts with long battery life or full featured parts versus salvageable parts for stratified feature sets
  4. Broader gains include complementing statistical process control / oversight over the prior operations such as wafer fab and assembly - has a trend been spotted that can result in immediate feedback / containment?
  5. Can systemic defects be found that result in a design iteration and/or process tune?
  6. Many aspects of test do and need to - increasingly be a part of design specifications - covering not just Design for Test (DFT) but also new efforts such as Design for Stress (DFS), Design for Diagnosability (DFD) and new types of telemetry for in-field aspects.
  7. Test program creation including Automated Test Pattern Generation (ATPG)
  8. New specifications - IEEE 1838 for chiplets used in today’s heterogenous packages
  9. Linking system level test and ATE test

Section 2 IC applications / Device types & test

Test flows, strategy and equipment need to be optimized for the application - there are many significant differences / needs across device types

  1. Sensors/actuators - MEMS & stimuli
  2. RF conducted vs radiated - AIP
  3. Memory, Logic, mixed signal, Analog, RF, power, Niches - SiC, GaN
  4. Systems – on a chip (SoC), on a board (SoB), in a package (SiP) - chiplet flows

Section 3 Basic test segments & flows

  1. Fab in-line tests (ex: gate oxide integrity), Class probe parametric
  2. Wafer probe test - Known Good Die (KGD) vs Known Tested Die (KTD)
  3. In Circuit Testing (ICT) - bed of nails
  4. Final test, System level test
  5. Pre / post burn-in & test during burn-in
  6. End of Line - packing media, ESD, MSL, bakes

Section 4 Test Types and Information / Actions

  1. Scalar vs Vector
  2. Stress testing
  3. Standard digital testing, SAF testing, IDDQ, timing, low voltage tests
  4. Shmoo plots
  5. Maps
  6. Repair, binning, grading
  7. Temperature

Section 5 Testers & Interface

  1. Testers - RF, mixed signal, analog, power, memory, logic, SoC
  2. Rack n stack, ATE, SLT, hybrid
  3. Load boards

Section 6 Probers, Handlers, Contacting

  1. Probers
    • Standard
    • Film frame
    • Special variants
    • Prober interface boards
  2. Handlers
    • Basic groups: Gravity, Turret, "Pick and Place" - corresponding drivers / packages
    • System level, Synchronous vs Asynchronous
    • Change kits
    • Handler interface boards
    • Assembly strips, Panel Level Processing (PLP)
    • Managing thermal (more on this in prober/handler section)
  3. Contacting
    • Probe cards
      • Standard PCB, Ceramic, Vertical probe cards, MEMS Microcantilever probe cards
    • Test sockets
    • Importance of maintenance and FPY (First Pass Yield)

Section 7 Data, Analytics and Action

  1. Data everywhere - reducing it to information for action
  2. Analytics
    • Outlier detection and algorithms
    • Adaptive test
    • End to end - Unit Level Traceability (ULT)
  3. Actions to take
  4. Future trends

Section 8 Putting it all together - silicon / product lifecycle management

Product lifecycle & test

  1. Lifecycle - new production introduction, ramp up, continuous improvement, ramp down
  2. Coverage/refinement, returns
  3. Test time reduction (TTR)
  4. Multi-site test xN - finding the sweet spot
  5. Test economics - including power of depreciated assets & typical cost / pricing factors

Section 9 Summary & Industry test challenges

  1. Summary
  2. Trends / Way Forward / Challenges
    • Combating silent data corruption SDC behaviors & root cause - and methods to address
    • How to increase observability in interconnections in chiplet designs
    • Physical probing <10um pitch (ex: hybrid bonding) - may be too messy - alternatives
    • 3D Heterogeneous Integration and Its Impact on Test
    • IEEE 1838 – bridging design & test
    • UCIe & "Bunch of Wires"
    • Improving unification across ATE & SLT for better coverage
    • Will all products use SLT in future? Should SLT be avoided or embraced?

Instructor Profile

Mark Berry

Christopher Henderson

Mark Berry is an independent consultant assisting startups in reducing the cost of test, implementing test strategies, accelerating new product introduction, and assisting test operations and business development. He also represents several test hardware, tester and test development firms. He has a deep understanding of high-volume semiconductor test.

His past roles have included process and device engineering roles at Motorola and Freescale. While at Motorola/Freescale, he was granted three device patents and authored several papers. He received the CEO Quality Award for radical improvements to FSRAM yield and reliability. This led to the Motorola’s first perfect 100% yielding wafer. He led large product and test operation teams across a wide spectrum of chips used in cellular phone applications – leading to 25 transceiver product qualifications across 7 technologies. His efforts helped to improve gross margins by 20%. Specifically, in the RF Power Amplifier module area, his efforts helped achieve a 60% cost reduction in 6 months. He is adept at taking products through concept, selection, definition, planning, execution, validation & ramp. Mark also sponsored a number of rotational engineers and enjoys teaching & mentoring.

He has also held executive leadership roles during his 14-year tenure at Amkor, leading worldwide test development across three sites. He maintained and implemented Amkor’s test equipment roadmap and regional test business development activities. He led global teams to implement complex advanced packaging flows (2.0/2.5/3D technologies) and devise optimum test flows for them. Finally, he worked at UTAC, leading their US business development team. He is familiar with a broad range of ATE & SLT testers, many types of handlers and probers, as well as contacting via probe cards and a wide variety of socket technology.

Mark has an MBA from St Edward’s University and a BSEE from the University of Illinois at Urbana-Champaign.