System Maintenance occurs every Friday.

Fundamentals of High-Volume Production Test

During a semiconductor product life cycle, there is a launch into high volume production test that provides sufficient test coverage to meet customer requirements, yet still meet cost targets. Design and test are closely linked, and there is a push to always implement test during the design process to determine what can be designed into the chip to fit seamlessly with test flows/outcomes. Products are typically guaranteed to meet performance in terms of design for testability, test coverage, and operational conditions such as voltage, frequency, and temperature. Test engineers must select automated test equipment (ATE), along with wafer probers, and packaged part handlers that can meet these requirements. There are many nuances to wafer probers and handlers depending on the wafer type and the package. There may be additional requirements associated with production test, such as accelerated life testing (burn-in), and system-level test (SLT). Many applications require testing across temperature and thermal management of dissipated power. All product lifecycles need to include continuous improvements to the point of diminishing return. For production testing, engineers primarily focus their efforts to improve test through test cost reduction and higher test coverage. Furthermore, production testing generates extremely high volumes of data, so the key is how to harvest this data and reduce it to meaningful information for action. This is a 2-day course that offers engineers insight into the Fundamentals of High-Volume Production Test. We focus on the test development process, choosing automated test hardware, and the analysis of test data, to provide the engineer with key insights into the successful fielding of high-volume semiconductor components that work properly in the customers application with high levels of quality.

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Course Dates | Location

May 20-21, 2024 | Phoenix, AZ

(Price available until Mon. Apr. 29)




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Refund Policy

If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

What Will I Learn By Taking This Class?

The course will cover the basic segments of today's high volume production test as found in Outsourced Assembly And Test contractors (OSATs), as well as internal Integrated Device Manufacturers (IDMs). Participants will learn basic, but powerful, aspects about the semiconductor industry. This skill-building series is divided into three segments:

  1. The Test Development Process. Engineers learn how balance the need for test coverage with the time it takes to perform the testing. Often, these two goals are at odds with one another.
  2. Choosing Appropriate Test Hardware. Test hardware (the ATE system, the handler or prober, and the interface boards) is expensive. Engineers need to choose the appropriate systems that meet the requirements for testing the semiconductor component without being too expensive.
  3. Analyzing Test Data. Engineers can gain a wealth of insight into a semiconductor component's performance, quality and reliability by examining the test data. However, the amount of test data generated is enormous. We will discuss strategies for what information should be extracted from the test data to provide these insights.

Course Objectives

  1. Participants will gain a greater understanding of their role in test development, the importance of test, and the link between design and design for test.
  2. Participants will gain an understanding of how test goals can differ by application and market segment.
  3. Participants will learn basic test elements and sequences used across the manufacturing process flow, which includes fab, bump, probe, and final test.
  4. The course covers the different types of test and their outcomes, along with appropriate actions that a test engineer should take.
  5. Participants will become familiar with the next steps after test.
  6. The course provides an overview of various test systems, material handling, and connections between the component and the tester (known as "contact").
  7. Participants will learn how to reduce test data to actionable information.
  8. Participants will learn how test supports continuous improvement over the semiconductor component lifecycle.
  9. The course covers the trends in test, as well as the future of test.

Course Outline

Day 1

  1. Introduction
    • Rationale
    • Value Added and Non-value Added Aspects of Test
    • Isolating Defective Parts
    • Triggering Repair Algorithms
    • Product Binning
    • Test as a Complement to Statistical Process Control
    • Oversight Over the Prior Operations (e.g., Wafer Fab and Assembly)
    • Detection of Systemic Defects
    • Design Aspects of Test: Design for Test (DFT), Design for Stress (DFS), Design for Diagnosability (DFD), Telemetry for In-field Aspects
    • Test Program Creation (i.e., Automated Test Pattern Generation (ATPG))
    • IEEE 1838 (e.g., Use of Standard for Chiplets)
    • Linking System Level Test and ATE test
  2. IC Applications / Device Types and Test
    • Sensors/Actuators - MEMS and Stimuli
    • RF - Conducted vs Radiated (e.g., Antenna in Package (AIP))
    • Memory, Logic, Mixed Signal, Analog, RF, Power, Niches (e.g., SiC, GaN)
    • Systems - On a Chip (SoC), On a Board (SoB), In a Package (SiP)
  3. Basic Test Segments and Flows
    • Fab Parametric In-line Tests
    • Wafer Probe Test - Known Good Die (KGD) vs Known Tested Die (KTD)
    • In Circuit Testing (ICT) (e.g., Bed of Nails)
    • Final Test, System Level Test
    • Pre/Post Burn-in and Test During Burn-in
    • End of Line - Packing Media, Electrostatic Discharge (ESD), Moisture Sensitivity Level (MSL), Non-Volatile Memory Bakes and Subsequent Testing
  4. Test Types, Information and Actions
    • Scalar vs Vector
    • Stress Testing
    • Standard Digital Testing, Stuck At Fault (SAF) Testing, Quiescent Power Supply Current (IDDQ), Timing, Low Voltage Tests
    • Shmoo Plots
    • Other Test Visualization Maps
    • Repair, Binning, Grading
    • Temperature

Day 2

  1. Testers and Interface Hardware
    • Testers - RF, Mixed-Signal, Analog, Power, Memory, Logic, SoC
    • Rack and Stack, ATE, SLT, Hybrid
    • Load boards
  2. Probers, Handlers, Contactors
    • Probers
      • Standard
      • Film frame
      • Special variants
      • Prober interface boards
    • Handlers
      • Basic groups: Gravity, Turret, "Pick and Place"
        • Corresponding Drivers
        • Packages
      • System Level - Synchronous vs Asynchronous
      • Change Kits
      • Handler interface boards
      • Assembly strips, Panel Level Processing (PLP)
      • Managing thermal (more on this in prober/handler section)
    • Contactors
      • Probe cards
        • Standard PCB, Ceramic, Vertical probe cards, MEMS Microcantilever Probe Cards
      • Test Sockets
      • Importance of Maintenance and FPY (First Pass Yield)
  3. Data, Analytics and Action
    • Data Everywhere - Reducing it to Information for Action
    • Analytics
      • Outlier Detection and Algorithms
      • Adaptive Test
      • End to End - Unit Level Traceability (ULT)
    • Actions to take
    • Future trends
  4. Putting It All Together - Product Lifecycle Management
    • Lifecycle - New Production Introduction, Ramp-up, Continuous Improvement, Ramp-down
    • Coverage/Refinement, Field Returns
    • Test Time Reduction (TTR)
    • Multi-site Testing - Finding the Sweet Spot
    • Test Economics (e.g., Power of Depreciated Assets, Typical Cost and Pricing Factors)
  5. Summary and Industry Test Challenges
    • Summary
    • Trends, Future Directions, Challenges
      • Combating Silent Data Corruption (SDC) Behaviors and Root Cause; and Methods to Address
      • How to Increase Observability in Interconnections in Chiplet Designs
      • Physical Probing <10um pitch (e.g., hybrid bonding) and Alternatives
      • 3D Heterogeneous Integration and Its Impact on Test
      • IEEE 1838 - Bridging Design and Test
      • UCIe and "Bunch of Wires"
      • Improving Unification Across ATE & SLT for Better Coverage
      • Future Uses of SLT and Its Advantages and Disadvantages

Instructor Profile

Mark Berry

Mark Berry

Mark Berry is an independent consultant assisting startups in reducing the cost of test, implementing test strategies, accelerating new product introduction, and assisting test operations and business development. He also represents several test hardware, tester and test development firms. He has a deep understanding of high-volume semiconductor test.

His past roles have included process and device engineering roles at Motorola and Freescale. While at Motorola/Freescale, he was granted three device patents and authored several papers. He received the CEO Quality Award for radical improvements to FSRAM yield and reliability. This led to the Motorola's first perfect 100% yielding wafer. He led large product and test operation teams across a wide spectrum of chips used in cellular phone applications - leading to 25 transceiver product qualifications across 7 technologies. His efforts helped to improve gross margins by 20%. Specifically, in the RF Power Amplifier module area, his efforts helped achieve a 60% cost reduction in 6 months. He is adept at taking products through concept, selection, definition, planning, execution, validation & ramp. Mark also sponsored a number of rotational engineers and enjoys teaching & mentoring.

He has also held executive leadership roles during his 14-year tenure at Amkor, leading worldwide test development across three sites. He maintained and implemented Amkor's test equipment roadmap and regional test business development activities. He led global teams to implement complex advanced packaging flows (2.0/2.5/3D technologies) and devise optimum test flows for them. Finally, he worked at UTAC, leading their US business development team. He is familiar with a broad range of ATE & SLT testers, many types of handlers and probers, as well as contacting via probe cards and a wide variety of socket technology.

Mark has an MBA from St Edward's University and a BSEE from the University of Illinois at Urbana-Champaign.