Electrostatic discharge is a 4 Billion (USD) a year problem for the Semiconductor Industry. This problem is likely to grow in the future as smaller devices are susceptible to damage at lower static voltages and latchup under more subtle conditions. Today, circuit designers and process integration engineers require a fundamental knowledge of device physics and electrothermal behavior of I/O structures in order to develop a process that is robust and can withstand the challenges of today’s varied environments in which ICs are fielded. Layout, ESD pulse behavior, semiconductor physics, and device modeling are all required to produce a successful product. Your industry needs competent engineers and scientists to help achieve these goals. ESD Design and Technology is a course that offers detailed instruction on a variety of subjects pertaining to ESD design and technology. This course is designed for every manager, engineer, and technician concerned with ESD at the I/O design level, the chip level, or supplying ESD tools and simulators to the industry.
(Includes this and other materials.)
Please email the printable registration form for online training to us at the email address on the form to complete your order.
Interested in a version of this course where you can ask questions in real time? Public and In-House versions of this course are available!
Participants learn to develop the skills to determine what constitutes a good ESD design, how to recognize devices that can reduce ESD susceptibility, and how to design new ESD structures for a variety of technologies.