System Maintenance occurs every Friday.
System Maintenance occurs every Friday.
Semiconductor packaging is becoming increasingly challenging. As integrated circuits increase in performance, new packaging techniques are required to remove the heat, handle the increased number of bondpads, and deal with the fragile Lo-K dielectrics used on these circuits. New technologies such as optoelectronics and microelectromechanical systems (MEMS) can require specialized packages. Smaller form factors require engineers to use higher density packaging options, like array packaging, chip scale packaging, and multi-chip modules. Although packaging can be a challenge, it can also provide a lower cost path for integration needs. For example, a system in a package design can be more cost effective than a system on a chip design. This section covers packaging technology issues, packaging design and modeling issues, as well as packaging reliability challenges.
$700
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Although we think of packaging as primarily an activity separate from the wafer itself, there are some wafer-related activities one typically performs with certain assembly flows and package types. For instance, it is quite common to backgrind, or thin, a wafer prior to packaging it. This is common for today's thin profile packages. Another common wafer-related activity is the redistribution layer and bump sequence. This is also performed at the wafer level prior to sawing the wafer apart. Even the wafer sawing operation can be thought of as a wafer-level activity.
Wafer Backgrinding/Thinning
Bump Processes
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This section covers the business environment and the technical drivers that affect semiconductor packaging. The relentless pursuit of Moore's Law by the semiconductor industry, the proliferation of packaging formats, and the introduction of new materials, have made packaging technology challenging in recent years. This section also provides an overview of these issues, and other issues, such as the rise of the system in a package (SIP) approach.
Business Trends and Drivers
ITRS Roadmap
Assembly and Packaging Processes Introduction
Business Trends and Drivers
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Lead-free electronics is fast becoming a reality. The pressure from the European Union, Japanese, and other legislative bodies almost guarantees that the industry will completely convert in the next several years. Right now, many manufacturers are using their lead-free components as a differentiator in the marketplace. The key challenges to going lead-free are technical and logistical in nature. On the technical side, the new solder alloys must be characterized for reliability performance. The surrounding materials must be able to withstand the higher reflow temperatures as well. On the logistics side, the conversion coordination will require a good deal of effort, since this involves schedules, supply lines, manufacturing processes, and other items. This section covers these issues in further detail.
Lead Free Issues
Lead Free Solders - General Issues
Lead Free Issues
Lead Free Solders - General Issues
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This material covers issues related to System on a Chip (SoC) and System in a Package (SiP). Both technologies have their advantages and disadvantages.
System-on-a-Chip vs. System-in-a-Package
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As the complexity of electronics increases, it is becoming more difficult to use a one size fits all approach to reliability and qualification. Instead, most manufacturers now use a market segmentation approach that takes into account the use conditions of a component. Different environments require different levels of reliability. Those same environments can affect reliability strongly. The approach used for reliability and packaging qualification is referred to as the knowledge-based reliability approach. This section covers this concept in more detail.
Use Conditions
Use Conditions
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This material covers low dielectric constant materials issues associated with the packaging process. Low-K materials are soft and have poor mechanical properties. This requires special approaches so that the packaging process does not damage these materials. Low-K materials also require special test techniques to monitor the affect of the packaging process on them.
Low-K Issues
Copper Low-k Impact on Package Reliability
Low-K Materials Properties - Part 1
Low-K Materials Properties - Part 2
Low-k Issues
Copper Low-k Impact on Package Reliability
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Polymers are increasingly important materials used in today's semiconductor packages. Polymers are used in the mold compounds, underfill materials, redistribution layer and bump dielectrics, and substrate materials. In this course we cover the fundamental properties of polymers, the uses for polymers in microelectronics, and some examples from real-world situations.
Mechanical Behavior of Solids
Polymers - Introduction
Polymers - Basic Properties
Polymer Case Studies
Specialty Polymers in Electronics
Polymers-Introduction
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Die connection is an important consideration for today's IC and semiconductor packages. Wire bonding and wafer bumping are the two major technologies for making connections between the die and the package leadframe or substrate. We discuss the materials and technologies used to join the die to the package in this section. We discuss topics like copper wire bonding, copper pillar bumping, through silicon vias, and more.
Cu Pillar Technology
Wire Bonding
Lead Finish and Trim, Solder Ball Attach
Bump Processes
Substrates
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Bond Shear
Wire Pull Test
This course discusses traditional processes used for packaging integrated circuits. This includes topics like: Wafer Saw, Leadframes, Die Attach, Wirebonding, Transfer Molding, Singulation, and Tape and Reel.
Die Attach
Leadframes
Dicing
Singulation
Packing and Shipping
Substrates
Underfills
Hybrid Microcircuit Packaging
Die Attach - Introduction
Die Attach - Temperature Issues
Hybrid Microcircuit Packaging
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