Semiconductor Package Design, Simulation, and Technology
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Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s microprocessor chips have one thousand times the processing power of those a decade ago. These challenges have been accomplished because of the integrated circuit industry’s ability to track something known as Moore’s Law. Moore’s Law states that an integrated circuit’s processing power will double every two years. This has been accomplished by making devices smaller and smaller.
The industry is also pushing to use semiconductor devices in an increasing array of applications. To accomplish this, the industry is also driving prices down. This has created a number of challenges related to the packaging of these components. This seminar is a 3-day course that offers detailed instruction on the technology issues (from design to manufacturing) associated with today’s semiconductor packages.
We place special emphasis on current package technology issues like lead-free solders, low-k dielectrics, and tools for package analysis. This course is a must for every manager, engineer, and technician working in semiconductor packaging, using semiconductor components in high performance applications or non-standard packaging configurations, or supplying packaging tools to the industry.
What Will I Learn By Taking This Class?
By focusing on current issues in packaging design, simulation, and technology, participants will learn why advances in the industry are occurring along certain lines and not others.
- The seminar will provide participants with an in-depth understanding of semiconductor packaging design and its technical issues.
- The seminar will provide participants with an in-depth understanding of semiconductor packaging technology and its technical issues.
- The participant will also be introduced to polymers, solders, and a host of materials being considered for advanced packaging.
- Participants will understand the basic concepts behind thermal and mechanical simulations of packages.
- The seminar will identify the key issues related to the continued growth of the semiconductor industry. This includes the need for high power dissipation and designs that can mitigate increasing die fragility because of low-k dielectrics.
- The seminar offers a wide variety of sample modeling problems that participants work in class to help them gain knowledge of the fundamentals of packaging modeling.
- Participants will be able to identify basic and advanced principles for mechanical stress and thermal diffusion.
- Participants will understand how package reliability, power consumption, and device performance are interrelated.
- Participants will be able to make decisions about how to construct and evaluate new packaging designs and technologies.
- Participants will also be introduced to wafer-level simulations, which are increasingly necessary with the advent of low-k dielectric.
- Package Technology
- Global Business Trends
- IC Technology and Implications on Packaging
- International Technology Roadmap for Semiconductors: What is it? What it says about Device Packaging?
- Package Design
- CAD software
- Design Check Rules
- Best Practices
- Packaging Materials
- Material science
- The Role of Polymers
- Failure Mechanisms
- Working with Package Subcontractors
- Who are they?
- Building the relationship
- What to expect
- Package Modeling
- Thermomechanical Modeling
- Thermal Modeling
- Process Modeling
- Package Reliability Simulations
- Advanced & Future Packages
- MEMS, Sensors, & Actuators
- 3D Wafer Level Packages
- LEDs, Solar Module Packages, etc.
Our courses are dynamic. We combine instruction by lecture, problem solving, and question/answer sessions to give you the tools you need to excel in packaging design and modeling. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. The course notes offer hundreds of pages of reference material that you can apply during your daily activities. Our instructors are internationally recognized experts. Our instructors have years of current and relevant experience in their fields. They're focused on answering your questions and teaching you what you need to know.
Steve Groothuis, M.S. Physics
Steve Groothuis received a Bachelor's in Physics (1983) from Michigan State University and Masters in Physics (1991) from the University of Texas. He began performing semiconductor package development, design, testing, and simulation in the Central Packaging Group, Texas Instruments in Dallas in 1983 as a Group Member of the Technical Staff. Prior to leaving TI, he managed the engineering staff in TI's Advanced Semiconductor Packaging Lab. In 1997, he was a Multiphysics Industry Specialist for ANSYS, Inc., defining Computer-Aided Engineering simulation software market plans, strategic accounts management, electronics packaging, MEMS device simulation initiatives, and product development for the electronics industry. From 2000-2008, he was with Micron Technology in positions from Senior Package Engineer in the Assembly and Packaging Department to Technology CAD and Analysis Manager in the Process RD Department at Micron Technology. His responsibilities included working with device and process simulations for new cell designs, supporting most aspects of semiconductor package simulations, and assessing new technology.
Currently, Mr. Groothuis is a Principal Consulting Engineer with SimuTech Group, Inc. He is actively involved in developing and winning new business opportunities for Finite Element Analysis (FEA) and Computational Fluid Dynamics (CFD) consulting projects. His efforts are focused on vertical markets such as Microelectronics, Semiconductor Packaging, Wafer Fabrication, NEMS/MEMS, Nanotechnology, Solar Energy, Wind Energy, and Consumer Electronics.
He has published over 30 papers at various conferences in semiconductor packaging, reliability, and numerical analysis. Mr. Groothuis is a Senior Member of the IEEE and has participated in ASME and JEDEC standards committees.