Semitracks, Inc.

Register for Upcoming Courses

To register online via credit card, please click the date of interest.

If you prefer to pay by purchase order or check, please fax the printable registration form for public courses to (505) 858-9813.For dates and locations in SE Asia, please contact KS Chuah at This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Refund Policy: If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

Course Overview

Semiconductor reliability is at a crossroads. In the past, reliability meant discovering, characterizing and modeling failure mechanisms and determining their impact on the reliability of the circuit. Today, reliability can involve tradeoffs between performance and reliability, assessing the impact of new materials, dealing with limited margins, etc. For today's complex ICs it is imperative that one consider reliability from the outset, during the design phase. Your company needs competent engineers and scientists who understand the predominant failure mechanisms and can translate these problems into requirements for IC design to minimize the likelihood of problems during manufacturing and use.

Design for Reliability is a 2 day course that offers detailed instruction on subjects pertaining to the impact of reliability on design. This course is designed for every manager, and engineer concerned with desiging new ICs, developing requirements, and interfacing with customers.

Participants learn to develop the skills to determine what failure mechanisms are important, how to model them, and how to design circuits to minimize their occurence.

1. Overview of Chip Reliability Issues: Participants learn what mechanisms tend to impact chip reliability, their distribution, and the operating environments that make them susceptible.
2. Failure Mechanisms: Participants learn the nature and manifestation of a variety of failure mechanisms that can occur both at the die level and at the package level. These include: time-dependent dielectric breakdown, hot carrier degradation, electromigration, stress-induced voiding, moisture, NBTI, soft errors, etc.
3. Layout Structures: Participants learn how standard cell and memory layouts can be manipulated to reduce susceptibility to particular failure mechanisms.
4. Design Strategies: Participants learn the basics on how to design ICs so that performance and reliability can be maximized for the customer's application.

Course Objectives

1. The seminar will provide participants with an in-depth understanding of the failure mechanisms, models, and design techniques used to achieve today’s high reliability components.
2. The seminar will identify the major failure mechanisms, explain how they are observed, how they are modeled, and how they are eliminated.
3. The seminar will introduce both architectural and layout techniques to reduce the impact of critical mechanisms like EM, NBTI, TDDB, and others.
4. Participants will be able to make tradeoffs between performance and reliability on semiconductor devices.
5. Participants will be able to identify appropriate software tools to purchase when starting and effort in this area.

Instructional Strategy

By using a combination of instruction by lecture, video, problem solving and question/answer sessions, participants will learn practical approaches to design for reliability. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. We use instructors who are internationally recognized experts in their fields that have years of experience (both current and relevant) in this field. The handbook offers hundreds of pages of additional reference material the participants can use back at their daily activities.

Course Outline

1. Reliability Concepts and Models
   • Concepts
   • Distributions
   • Exponential
   • Normal
   • Lognormal
   • Weibull
2. Electrostatic Discharge, ESD
   • Failure modes
   • Models
   • Testing
   • Process and device guidelines
3. Gate Stack
   • Surface and interface effects
   • Gate dielectric integrity, TDDB, QBD, SILC
   • High-K issues, Poly-gate, metal gates
   • Failure models, accelerated stress-test, lifetime projections
   • Process and device guidelines
4. Hot-Carrier Reliability
   • Physics, models
   • Failure modes, MOSFETs, CMOS, BiCMOS
   • Accelerated stress-test, lifetime projections
   • Process and device guidelines
5. Latch-up
   • Physics, model
   • CMOS failure modes
   • Testing
   • Process and devices guidelines
6. Bias-Temperature Instabilities, BTI
   • Mobile ions; NBTI, PBTI
   • CMOS failure modes
   • Models
   • Accelerated stress tests; lifetime projections
   • Process and devices guidelines
7. Single-Event Upsets, SEU
   • Energetic particles
   • Soft errors, memory, logic
   • Accelerated stress tests
   • Process and devices guidelines
   • VIII.Electro- and Stress-Migration
   • Aluminum, copper
   • ILD, low-K
   • Models
   • Accelerated stress-tests; lifetime projections
   • Process and device guidelines
8. Burn-in
   • Need
   • Strategies
   • Tradeoffs

Our instructors are world-renowned in their areas of expertise. All of our instructors have years of industrial experience, giving them unique insight into the topics they teach. Also, our instructors are experienced at teaching and enjoy imparting their knowledge and insight to you the attendee. If you have questions about our instructors, please contact us for further information.