ESD and Latchup Design and Technology

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Course Dates	Cost
June 14-15, 2010, Boston, MA, USA (books included)	$1495 $1395 until May 24

If you prefer to pay by purchase order or check, please fax the printable registration form for public courses to (505) 858-9813. If you can't make the above course dates or locations, click here to request a date and/or location for this course. For dates and locations in SE Asia, please contact KS Chuah at This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Refund Policy: If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

Course Overview

Electrostatic discharge (ESD) costs the semiconductor industry over $4 billion (USD) a year. This problem is likely to grow in the future as smaller devices are susceptible to damage at lower static voltages and latchup under more subtle conditions. Today, circuit designers and process integration engineers must have a fundamental knowledge of device physics and electrothermal behavior of I/O structures in order to develop a process that is robust and can withstand the challenges of today’s varied IC fielding environments. Layout, ESD pulse behavior, semiconductor physics, and device modeling are all required to produce a successful product. The industry needs competent engineers and scientists to help achieve these goals. ESD Design and Technology is a 2 to 4 day course that offers detailed instruction on a variety of subjects pertaining to ESD design and technology. This course is designed for every manager, engineer, and technician concerned with ESD at the I/O design or chip level or supplying ESD tools and simulators to the industry.

Participants learn to develop the skills to determine what constitutes a good ESD design, how to recognize devices that can reduce ESD susceptibility, and how to design new ESD structures for a variety of technologies.

Overview of the ESD Failure Mechanism: Participants learn the fundamentals of ESD, the physics behind overstress conditions, test equipment, test protocols, and the results of failure.
ESD Technology Issues: Participants learn the behavior of different IC technologies under various ESD stress conditions. This includes CMOS, bipolar, BiCMOS, SOI GaAs, SiGe, SiGe:C and other strained silicon technologies. Participants also study the response of an IC’s substrates, wells, junctions, dielectric layers, and metallization to ESD.
ESD Circuit Design Issues: Participants learn how designers develop circuits to protect against ESD damage. This includes MOSFETs, diodes, off-chip driver circuits, receiver circuits, and power clamps.
Test Strategies: Participants learn the basics on how to test design screening tests and test structures and perform burn-in testing effectively.

Course Objectives

The seminar will provide participants with an in-depth understanding of the ESD failure mechanism, test structures, equipment, and testing methods used to achieve robust ESD resistance in today’s components.
Participants will be able to gather ESD data, determine how best to plot the data, and make inferences from that data.
The seminar will identify the major issues associated with ESD and explain how they occur, how they are modeled, and how they are mitigated.
The seminar can be offered with several textbooks that cover the topic of ESD in much greater detail. The course author is a recognized expert in the field and has written the definitive textbook series on ESD.
Participants will be able to identify basic ESD structures and how they are used to help reduce ESD susceptibility on semiconductor devices.
Participants will be able to knowledgeably design ESD structures that are appropriate to assure the robustness of a component.
Participants will be able to identify appropriate tools to purchase when starting or expanding ESD test capabilities.

Instructional Strategy

By using a combination of instruction by lecture, written text material, problem solving and question/answer sessions, participants will learn practical approaches to the failure analysis process. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. Our instructors are internationally recognized experts in their fields and have years of both current and relevant experience. The textbooks offer hundreds of pages of additional reference material participants can apply during their daily activities.

Course Outline

Educational Materials

$300 combined value... free with the price of registration!

ESD: Physics and Devices

By Steven H. Voldman

This volume is the first in a series of three books addressing Electrostatic Discharge (ESD) physics, devices, circuits and design across the full range of integrated circuit technologies. ESD Physics and Devices provides a concise treatment of the ESD phenomenon and the physics of devices operating under ESD conditions. Voldman presents an accessible introduction to the field for engineers and researchers requiring a solid grounding in this important area. The book contains advanced CMOS, Silicon On Insulator, Silicon Germanium, and Silicon Germanium Carbon. In addition it also addresses ESD in advanced CMOS with discussions on shallow trench isolation (STI), Copper and Low K materials.

Provides a clear understanding of ESD device physics and the fundamentals of ESD phenomena.
Analyses the behaviour of semiconductor devices under ESD conditions.
Addresses the growing awareness of the problems resulting from ESD phenomena in advanced integrated circuits.
Covers ESD testing, failure criteria and scaling theory for CMOS, SOI (silicon on insulator), BiCMOS and BiCMOS SiGe (Silicon Germanium) technologies for the first time.
Discusses the design and development implications of ESD in semiconductor technologies.

An invaluable reference for EMC non-specialist engineers and researchers working in the fields of IC and transistor design. Also, suitable for researchers and advanced students in the fields of device/circuit modelling and semiconductor reliability.

ESD: Cicuits and Devices

By Steven H. Voldman

ESD Circuits and Devices provides a clear insight into the layout and design of circuitry for protection against electrical overstress (EOS) and ESD. With an emphasis on examples, this text:

explains ESD buffering, ballasting, current distribution, design segmentation, feedback, coupling, and de-coupling ESD design methods;
outlines the fundamental analytical models and experimental results for the ESD design of MOSFETs and diode semiconductor device elements, with a focus on CMOS, silicon on insulator (SOI), and Silicon Germanium (SiGe) technology;
focuses on the ESD design, optimization, integration and synthesis of these elements and concepts into ESD networks, as well as applying within the off-chip driver networks, and on-chip receivers; and
highlights state-of-the-art ESD input circuits, as well as ESD power clamps networks.

Continuing the author’s series of books on ESD, this book will be an invaluable reference for the professional semiconductor chip and system ESD engineer. Semiconductor device and process development, quality, reliability and failure analysis engineers will also find it an essential tool. In addition, both senior undergraduate and graduate students in microelectronics and IC design will find its numerous examples useful.

Instructor Profile

Dr. Steven H. Voldman

Steven H. Voldman was the first IEEE Fellow for electrostatic discharge (ESD) protection in semiconductors. In 2007, he received the ESD Association Outstanding Contribution Award. Voldman is an IEEE Electron Device Society (EDS) Distinguished Lecturer. He received his B.S. Engineering Science (1979) from University of Buffalo, M.S. EE (1981) from Massachusetts Institute of Technology (MIT); a second degree EE Degree (Engineer Degree) from MIT; a MS Eng. Physics (1986) and a Ph.D EE (1991) from Univ. of Vermont under IBM's Resident Study Fellow program.

Voldman’s work at IBM for 25 years included fundamental research of ESD and latchup in advanced CMOS, SOI, SiGe, power electronics, image processing as well as magnetic recording (MR) disk drive industry. Voldman provided experimental research, invention, chip design integration, circuit design, CAD methodology, customer support, to strategic planning, for latchup since 1984, and ESD since 1991. In Qimonda, Voldman supported 110, 78, 58 and 48 nm CMOS technology ESD design. In TSMC, Voldman supported 45 nm and sub-45 nm ESD and latchup design and technology. Dr. Voldman was chairman of the SEMATECH ESD Working Group (1995-2000), to establish a national strategy for ESD in the United States. He is a member of the ESD Association Board of Directors, ESDA Education Committee, ESD Technology Roadmap Committtee, as well ESD Standards Chairman for Transmission Line Pulse testing. In 2009, he is presently a member of the ESD Board of Directors (2009-2012), and General Chairman of the ESD Symposium 2009. As an ESD Association Board of Director, Voldman initiated the “ESD on Campus” program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 30 universities in the United States, Singapore, Taiwan, Malaysia, Philippines, Thailand, and China.

Voldman has provided tutorials internationally on ESD, and CMOS latchup, as well as tutorials on innovation, invention and patenting. He is a recipient of over 175 issued US patents and 110 US patent applications; in IBM, Voldman was awarded the IBM Master Inventor Award. Dr. Voldman has written over 150 publications, and has written for Scientific American. Dr. Voldman is an author of the first ESD textbook series; ESD: Physics and Devices (2004), ESD: Circuits and Devices (2005), a third book, ESD: Radio Frequency (RF) Technology and Circuits (2006), and fourth companion text, Latchup, in 2007.

In 2008, Voldman formed Dr. Steven H. Voldman LLC (limited liability corporation), where he provides expert witness / litigation support, instruction, and consulting. Voldman served as an expert witness for the Hewlett Packard vs Acer case in 2008. In 2008, Voldman also supported Taiwan Semiconductor Manufacturing Corporation (TSMC) headquarters in Hsinchu, Taiwan.

Semitracks, Inc.