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Home Courses Public Courses IC Packaging Design and Modeling

IC Packaging Design and Modeling

Instructor: Dr. Steve Groothuis

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Course Dates Cost
August 9-11, San Jose, CA, USA
 $1595

If you prefer to pay by purchase order or check, please fax the printable registration form for public courses to (505) 858-9813. If you can't make the above course dates or locations, click here to request a date and/or location for this course. For dates and locations in SE Asia, please contact KS Chuah at This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Refund Policy: If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

Course Overview

Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s microprocessor chips have one thousand times the processing power of those a decade ago. These challenges have been accomplished because of the integrated circuit industry’s ability to track something known as Moore’s Law. Moore’s Law states that an integrated circuit’s processing power will double every two years. This has been accomplished by making devices smaller and smaller. The industry is also pushing to use semiconductor devices in an increasing array of applications. To accomplish this, the industry is also driving prices down. This has created a number of challenges related to the packaging of these components. Semiconductor Packaging Design is a 3-day course that offers detailed instruction on the design and modeling of semiconductor packages. We place special emphasis on package interactions with the die. This course is a must for every manager, engineer, and technician working in semiconductor packaging, using semiconductor components in high performance applications or non-standard packaging configurations, or supplying packaging tools to the industry.

By focusing on the fundamentals of packaging design and modeling, participants will learn why advances in the industry are occurring along certain lines and not others. Our instructors work hard to explain semiconductor packaging without delving heavily into the complex physics and materials science that normally accompany this discipline.

Participants learn basic but powerful aspects about the semiconductor packaging. This skill-building series is divided into four segments:

  1. Packaging Design Overview: Participants learn the fundamentals of packaging design. They learn why modeling has become critical to semiconductor packaging for today’s designs.
  2. Mechanical Simulations: Participants learn the fundamentals of displacement, strain, stress, and energy. They learn how to leverage St. Venant’s Principle and apply fracture mechanics to a problem.
  3. Thermal Simulations: Participants learn heat transfer modeling. They also learn about steady-state and transient thermal modeling. The instructor also explains industry standard and compact thermal models.
  4. Modeling Semiconductor Packages: Participants learn about the software used for modeling a variety of aspects of semiconductor packaging. They see a number of examples of current modeling tools used by package design experts.

Course Objectives

  1. The seminar will provide participants with an in-depth understanding of semiconductor packaging design and its technical issues.
  2. Participants will understand the basic concepts behind thermal and mechanical simulations of packages.
  3. The seminar will identify the key issues related to the continued growth of the semiconductor industry. This includes the need for high power dissipation and designs that can mitigate the increasing fragility of the die because of low-k dielectrics.
  4. The seminar offers a wide variety of sample modeling problems that participants work in class to help them gain knowledge of the fundamentals of packaging modeling.
  5. Participants will be able to identify basic and advanced principles for mechanical stress and thermal diffusion.
  6. Participants will understand how package reliability, power consumption, and device performance are interrelated.
  7. Participants will be able to make decisions about how to construct and evaluate new packaging designs and technologies.
  8. Participants will also be introduced to wafer-level simulations, which are increasingly necessary with the advent of low-k dielectrics.

Instructional Strategy

By using a combination of instruction by lecture, classroom exercises, and question/answer sessions, participants will learn practical information on semiconductor packaging and the operation of this industry. From the very first moments of the seminar until the last sentence of the training, the driving instructional factor is application. Our instructors are internationally recognized experts in their fields and have years of both current and relevant experience.

Course Outline

  1. Package Design Principles
    1. Background
    2. ITRS Roadmap Issues
    3. JEDEC Standards for Packaging
    4. Semiconductor Package Designs: What is a Good Packaging Design?
    5. Modeling Software
  2. Assembly and Packaging Processes
    1. Assembly and Packaging Processes
    2. Selecting Package Materials
    3. Advanced Packaging
    4. Stacked Die & Stacked Packages
    5. Through Silicon Via (TSV) Interconnects
  3. Stress Simulations
    1. Solid Mechanics Concepts
      1. Basics of Displacement, Strain, Stress and Energy
      2. Leveraging St. Venant’s Principle
      3. Applying Fracture Mechanics
    2. Manufacturability
      1. Thermomechanical Modeling Metrics
      2. To Model or Not to Model
      3. Assembly Process Simulations
  4. Thermal Simulations
    1. Heat Transfer Principles
    2. JEDEC Thermal Test and Simulations
    3. Steady-State and Transient Thermal Modeling
    4. Application-Specific Thermal Simulations
    5. Using Compact Thermal Models
  5. Reliability and Coupled Mechanics
    1. Thermomechanical Reliability
      1. Solder Joint Reliability (SJR)
      2. Single Chip & Multiple Chip Package SJR
      3. Solder Joint Shape Predictions
    2. Coupled Mechanics
      1. Moisture Diffusion
      2. Plastic Package “Popcorn” Cracking
  6. Wafer-Level Simulations
    1. Venturing into New Territory (Submodeling)
    2. Chip-Package Interactions
      1. Interfacial Fracture Mechanics
      2. Bridging IC Interconnect and Package Gaps
    3. Microelectromechanical Systems (MEMS)
      1. Device Operations
      2. MEMS Packaging
  7. Drop Tests Simulations
    1. Drop Test & Structural Dynamics
    2. Solder Selection & Performance
      1. Leaded Solders
      2. Lead-Free Solders
      3. Surface Finishes, Solder Pastes, & Metallization
    3. Package Design Effects
      1. Stand-Off Heights
      2. Ball Array Pattern
      3. Single Chip & Multiple Chip Packages

Course Overview

Instructor Profile

Mr. Steve Groothuis, Micron Technology Inc.

Mr. Groothuis received a Bachelors in Physics (1983) from Michigan State University and Masters in Physics (1991) from the University of Texas. He began work in the Central Packaging Group, Texas Instruments, Dallas in 1983 as a Group Member of the Technical Staff performing semiconductor package development, design, testing, and simulation. Prior to leaving TI, he managed the engineering staff in TI's Advanced Semiconductor Packaging Lab. In 1997, he was a Multiphysics Industry Specialist for ANSYS Inc. defining Computer-Aided Engineering simulation software market plans, initiatives, and product development for the Electronics Inudstry. He is currently a Corporate Fellow at Micron Technology Texas LLC. Mr. Groothuis is a member of the IEEE, ASME, and several JEDEC standards committees.