Semitracks, Inc.

Instructor: Dr. Roger Stierman

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Refund Policy: If a course is canceled, refunds are limited to course registration fees. Registration within 21 days of the course is subject to $100 surcharge.

Course Overview

Semitracks, Inc. and SHRDC have put together a course which will provide an overview of the current business climate, anticipated trends, and the associated impact on assembly/packaging roadmaps. There will be an in-depth discussion of both high-end CPU roadmaps plus the roadmaps to address the multitude of communications and network devices that are driving the digital revolution. The course will generically address typical assembly flows and cost implications for both wafer fabrication and assembly with special focus on what the low-cost alternatives will be in both camps.

Based on the technical reliability issues that the packaging roadmaps drive, such as thin film delamination/cracking, bump cracks, via delamination/cracking, thermal interface degradation, heat sink retention, and socketing issues, there will be a review of commonly used failure analysis tools and techniques appropriate to each failure mechanism. Thus, state of the art non-destructive imaging tools of acoustics, x-ray, scanning SQUID microscopy, and terahertz imaging will be reviewed with respect to advantages, limitations, and likely evolution to next generation. Other techniques that will be discussed are time domain reflectometry (TDR), adhesion testing, thin film materials characterization, and disassembly techniques to allow fault isolation and failure analysis. There will be discussion of the impact of next generation technologies such as Cu, ultra low-k dielectrics, 300mm wafer fabrication, wafer scale packaging, embedded passives, chip on board, and modular integration.

Finally, the course will hint at the future, focusing on Nanotechnology, Connectintelligence, and the currently ill thought-out arena of what packaging/assembly even means for this era of molecular devices. The course will also cover metallurgy of metals such as connectors, sealants, thermal interface materials (TIMs), and shock absorbers. There will be discussion on the metallurgy of solders in the lead free solders, under-bump metallization (UBM), solder joint cracks, ILD damage, metallurgical implications, electromigration comparisons of Al, Cu and solders, tin whiskers in lead-free applications, and many more.

This course is recommended for engineers and scientists involved in setting the direction for adapting to the rapidly exploding arena of assembly/packaging in the digital revolution. This course will also be especially useful to engineers and scientists actively engaged in performing risk assessments on packaging technologies, performing fault isolation and failure analysis and performing stressing to achieve reliability certification of such technologies. Technical managers/engineers in package design, advanced packaging, assembly process, QRA/failure analysis, reliability, material & process, and anyone wanting to enhance their knowledge in packaging design will benefit from this course.

• General trends in assembly and packaging technology: The participants will learn the historical and forecast trends in packaging and assembly, including the response to the current business climate, the specifics of what the CPU and Non-CPU roadmaps look like, and how they link to the Sematech ITRS roadmap.
• Package reliability: The presenters will provide a detailed description of the technical reliability issues attendant to the future technical trends and the challenges they create for failure/materials analysis in terms of tools and techniques.
• Package analysis: The presenters will provide a considered overview of the state of the art tools and techniques and what is projected for the next generation tool suite. This will include the work of the AAF, Sematech’s Assembly Analytical Forum which addresses several specific gaps.
• New opportunities: The presenters will set the stage for the brave new world of Nanotechnology and connect intelligence with its as yet vaguely defined assembly requirements.

Course Overview

Instructor Profile

Dr. Roger Stierman

Dr. Roger Stierman is an independent consultant who focuses on packaging issues and analysis techniques. Roger received his B.S degree in Physics from Loras College and M.S and Ph.D. degrees in Metallurgy from Iowa State University. During his 25-year career at Texas Instruments, he developed processes for semiconductor package assembly and characterized semiconductor packaging materials such as die attach, mold compounds, polymer overcoats, wire bond and flip chip connections, flip chip underfills, and package-to-PWB attachment. As manager of the Semiconductor Packaging Lab, he delivered training for physical failure analysis methods including precision cross-sectioning, SEM/EDS, X-Ray, tensile and 4-point bend testing, microhardness, RIE/ICP etching, ion milling and laser decapsulation. Currently, he works at Omniprobe Inc. and consults on semiconductor packaging failure analysis.