Instructors: Dr. Jeffrey Gambino

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Course Overview

Semiconductor reliability is at a crossroads. In the past, reliability meant discovering, characterizing and modeling failure mechanisms and determining their impact on the reliability of the circuit. Today, reliability can involve tradeoffs between performance and reliability, assessing the impact of new materials, dealing with limited margins, etc. Analysis and experimentation must now account not only for material interactions on the die, but also package interactions with the die. This requires knowledge of subjects like: IC processing, new materials and materials science, chemistry, and customer expectations. While reliability levels are at an all-time high level in the industry, rapid changes may quickly cause reliability to deteriorate. Your company needs competent engineers and scientists to help solve these problems. Reliability and Characterization Challenges for Advanced ICs is a 1-day course that offers detailed instruction on a variety of subjects pertaining to semiconductor reliability and characterization. This course is designed for every manager, engineer, and technician who develops new processes, must understand Front End of the Line integration, packaging interactions with the die, and reliability conditions. Engineers involved in reliability, product engineering, wafer manufacturing, assembly, using semiconductor components, or supplying tools to the industry can all benefit from this course.

Course Objectives

1. The seminar will provide participants with an in-depth understanding of the transistors, interconnect and dielectric materials used in today’s advanced components.
2. Participants will be able to understand the properties of materials and how they affect the IC.
3. The seminar will identify the major failure mechanisms, explain how they are observed, how they are modeled, and how they are eliminated.
4. Participants will be able to identify current reliability issues, how they impact the materials choices for the IC, and how they impact the overall reliability of the IC.

Course Outline

1. Introduction
   1. Scaling and Its Impact on Reliability
2. Time Dependent Dielectric Breakdown
   1. Energy, Current, Voltage, Electric Field Dependencies
   2. Models
   3. Dealing with Soft Breakdown
   4. Dealing with Hi-K Materials
   5. Statistical Implications and Circuit Level Modeling
3. Hot Carrier Effects
   1. Physical Behavior
   2. Models for Low, Medium, and High Gate Voltage
   3. P-channel and N-channel Effects
   4. Implications at the Circuit Level
4. Negative Bias Temperature Instability
   1. Mechanism
   2. Fast Measurement Techniques
   3. Reaction-Diffusion Model
   4. New Thinking on Models
   5. Circuit Level Modeling and Behavior
5. Positive Bias Temperature Instability and Hi-K
   1. Hi-K Materials Behavior
   2. Fast Measurement Techniques
   3. PBTI Model
   4. Circuit Level Modeling and Behavior
6. Low-κ Materials
   1. What is K?
   2. Low-κ (organic vs inorganic)
   3. Porosity
   4. Barrier layers (SiN; SiC)
   5. Electrical properties
   6. Mechanical properties
   7. Thermal properties
   8. Thermal and Chemical stability
7. Integration of Cu with Low-κ Materials
   1. Integration options
   2. Effective K
   3. Patterning
   4. Cleans
   5. Metal deposition
   6. CMP
   7. Packaging
8. Reliability of Cu Interconnects in Low-k Materials
   1. Electromigration
   2. Stress migration
   3. Oxidation
   4. TDDB
   5. Package reliability
   6. Intrinsic vs extrinsic fails
9. Future Reliability Challenges

Instructor Profile

Dr. Jeffrey Gambino

Dr. Gambino received his B.S. degree in materials science from Cornell University, Ithaca, NY, in 1979, and his Ph.D. degree in materials science from the Massachusetts Institute of Technology, Cambridge, MA, in 1984. He joined IBM, Hopewell Junction, NY, in 1984, where he worked on silicide processes for Bipolar and CMOS devices. In 1992, he joined the DRAM development alliance at IBM's Advanced Semiconductor Technology Center, Hopewell Junction, NY. While there, he developed contact and interconnect processes for 0.25-, 0.175-, and 0.15-mm DRAM products. In 1999, he joined IBM's manufacturing organization in Essex Junction, VT, where he has worked on copper interconnect processes for CMOS logic technology. He has published over 90 technical papers and holds over 100 patents.