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Leading Edge Design Tradeoffs

Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s microprocessor, graphics, and AI processing chips have one thousand times the processing power of those a decade ago. These challenges have been accomplished due to the integrated circuit industry’s ability to track something known as Moore’s Law. Moore’s Law states that an integrated circuit’s processing power will double every two years. This has been accomplished by making devices smaller and smaller. The question looming in everyone’s mind is “How far into the future can this continue?” Leading Edge Design Tradeoffs is an 8 hour course that offers detailed instruction on the processing used in a modern integrated circuit, and the tradeoffs engineers and scientists must make in order to reliably manufacture state-of-the-art integrated circuits. We place special emphasis on current issues related to manufacturing the next generation devices. This course is a must for every manager, engineer and technician working in the semiconductor industry, using semiconductor components, or supplying tools to the industry.

By concentrating on the latest developments in silicon integrated circuit technology, participants will learn why tradeoffs are becoming critical at feature sizes below 20nm. Our instructors work hard to explain semiconductor processing without delving heavily into the complex physics and materials science that normally accompany this discipline.

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Item

1-Year Online Training Subscription

(Includes this and other materials.)

Cost

$700

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Please email the printable registration form for online training to us at the email address on the form to complete your order.

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What Will I Learn By Taking This Class?

Participants will learn basic, but powerful, aspects about integrated circuit fabrication technology. They will focus on understanding impacts on performance, understanding basics of what may happen if something is incorrect or pushing a design limit, and knowing what to consider and ask for when working with designers on issues and improvements.  This skill-building series is divided into four segments:

  1.  Transistor Performance Overview. Participants will study the major factors associated with transistor performance, and the options available to adjust that performance.
  2. Process Design Kits Overview.  Participants will learn about the elements of a modern process design kit, what those elements communicate about the process technology, and what may be possible in a chip design.
  3.  Performance Simulation Overview. Participants will learn how one simulates the performance of a complex integrated circuit with activities such as parametric extraction for transistor performance, static timing analysis, etc.
  4.  Process Corners and Limitations. Participants will study the behavior of transistors, and how they define an envelope of operation for a design.  This includes various voltage levels and sizings for transistors.

Course Objectives

  1. This course will provide participants with an in-depth understanding of a number of elements related to chip design, considering the use of a state-of-the-art process, like Process Design Kits (PDKs), design rules, timing analysis, and other elements.
  2. Participants will understand how processing at the transistor level relates to transistor performance, and ultimately, product behavior.
  3. Participants will also understand how decisions are made concerning transistor sizing, transistor balancing, performance and power dissipation.
  4. This course will provide a look into the 7nm design process as an example to illustrate the necessary tradeoffs.
  5.  Participants will understand the relationship between design, process, and yield.
  6. Participants will be able to make decisions concerning tradeoffs that the foundry might be willing to offer, and what tradeoffs are likely to emerge in the coming years.

Course Contents

Leading Edge Design Tradeoffs

  • Leading Edge Design Tradeoffs Forum
  • Announcements

Courses

  • Introduction
  • Device Physics
  • Process Design Kits
  • Parameter Extraction
  • FinFET Design - Lithography
  • 7nm Design Concepts
  • Static Timing Analysis
  • Design Rules
  • Yield Data
  • Process Corners
  • Thermal Design Power
  • Work Function Metals for Gate
  • Leading Edge Design Tradeoffs Final Test
  • Leading Edge Design Tradeoffs Certificate

Documents

  • Design Tradeoffs Introduction
  • Device Physics - Part 1
  • Device Physics - Part 2
  • Process Design Kits
  • Parameter Extraction
  • FinFET Design - Lithography
  • 7nm Design Concepts - Part 1
  • 7nm Design Concepts - Part 2
  • Static Timing Analysis
  • Design Rules
  • Yield Data
  • Process Corners
  • Work Function Metals for Gate
  • Thermal Design Power