System Maintenance occurs every Friday.

Leading Edge Process Tradeoffs

Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today’s microprocessor, graphics, and AI processing chips have one thousand times the processing power of those a decade ago. These challenges have been accomplished because of the integrated circuit industry’s ability to track something known as Moore’s Law. Moore’s Law states that an integrated circuit’s processing power will double every two years. This has been accomplished by making devices smaller and smaller. The question looming in everyone’s mind is “How far into the future can this continue?” Leading Edge Process Tradeoffs is an 8 hour course that offers detailed instruction on the fabrication process used in a modern integrated circuit, and the tradeoffs engineers and scientists must make in order to reliably manufacture state-of-the-art integrated circuits. We place special emphasis on current issues related to manufacturing the next generation devices. This course is a must for every manager, engineer and technician working in the semiconductor industry, using semiconductor components or supplying tools to the industry.

By concentrating on the latest developments in silicon integrated circuit technology, participants will learn why tradeoffs are becoming critical at feature sizes below 20nm. Our instructors work hard to explain semiconductor processing without delving heavily into the complex physics and materials science that normally accompany this discipline.

Register for an Account

Item

1-Year Online Training Subscription

(Includes this and other materials.)

Cost

$700

Pay Via Credit Card

Add To Shopping Cart

Pay Via Purchase Order/Check

Please email the printable registration form for online training to us at the email address on the form to complete your order.

Additional Information

Refund Policy

What Will I Learn By Taking This Class?

Participants will learn basic, but powerful, aspects about integrated circuit fabrication technology. They will focus on understanding impacts on performance, understanding basics of what may happen if something is incorrect or pushing a design limit, and knowing what to consider and ask for when working with process engineers on issues and improvements.  This skill-building series is divided into three segments:

  1. Front End Of Line (FEOL) Overview. Participants will study the major developments associated with FEOL processing, including Ion Implantation, Rapid Thermal Annealing (RTA) for implants and silicides, and Pulsed Plasma Doping. They will also study alternate substrate technologies like SOI, as well as High-k/Metal Gates for improved leakage control.
  2. Back End Of Line (BEOL) Overview.  Participants will study the major developments associated with BEOL processing, including copper metallization and Low-k Dielectrics.  They will learn about why they’re necessary for improved performance.
  3. FinFET Manufacturing Overview. Participants will learn how semiconductor manufacturers are currently processing FinFET devices and the difficulties associated with three-dimensional structures from a processing and metrology standpoint.

Course Objectives

  1. This course will provide participants with an understanding of Bulk technology, SOI technology and the technical issues.
  2. Participants will understand how Hi-K/Metal Gate devices are manufactured.
  3. Participants will understand how FinFET devices are manufactured.
  4. This course will provide a look into the latest challenges with copper metallization and Low-k dielectrics.
  5. Participants will understand the difficulties associated with non-planar structures and methods to alleviate the problems.
  6. Participants will be able to make decisions about how to evaluate FinFET devices and what changes are likely to emerge in the coming years.
  7. Participants will see a comparison between FinFETs and new alternatives (such as Gate All Around (GAA) structures and nanosheets).

Course Contents

Leading Edge Process Tradeoffs

  • Leading Edge Process Tradeoffs Forum
  • Announcements

Courses

  • Introduction
  • FinFET Manufacturing - Layout
  • FinFET Manufacturing - Process Flow
  • Example FinFET Processes
  • Lithography
  • Isolation
  • Implant and Anneal
  • Strain Engineering
  • Hi-K Metal Gates
  • Back End Of Line - Performance
  • Back End Of Line - Contacts
  • Back End Of Line - Copper
  • Back End Of Line - Low-K Dielectrics
  • Leading Edge Process Tradeoffs Final Test
  • Leading Edge Process Tradeoffs Certificate

Documents

  • Process Tradeoffs Introduction
  • FinFET Manufacturing - Layout
  • FinFET Manufacturing Process Flow
  • Example FinFET Processes
  • Lithography
  • Isolation
  • Implant and Anneal
  • Strain Engineering
  • Hi-K Metal Gates
  • Back End Of Line - Performance
  • Back End of Line - Contacts
  • Back End of Line - Copper
  • Back End of Line - Low-k Dielectrics